PIC18F2431-E/SP Microchip Technology, PIC18F2431-E/SP Datasheet - Page 297

• Manufacturer Part Number: PIC18F2431-E/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-E/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3AC164035 - MODULE SKT FOR 18F2X31 28SOICDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction:
After Instruction:
Decode
PORTC =
PORTC =
Q1
register ‘f’
Bit Toggle f
[ label ] BTG f,b[,a]
0  f  255
0  b < 7
a [0,1]
(f<b>)  f<b>
None
Bit ‘b’ in data memory location, ‘f’, is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value.
1
1
BTG
Read
0111
Q2
0111 0101 [0x75]
0110 0101 [0x65]
PORTC,
bbba
Process
Data
Q3
4
ffff
register ‘f’
PIC18F2331/2431/4331/4431
Write
Q4
ffff
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Overflow
If Overflow
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Overflow
[ label ] BOV
-128  n  127
if Overflow bit is ‘1’,
(PC) + 2 + 2n  PC
None
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
address (HERE)
1;
address (JUMP)
0;
address (HERE + 2)
0100
BOV
operation
Process
Process
n
Data
Data
No
Q3
Q3
DS39616D-page 297
JUMP
nnnn
operation
operation
Write to
PC
No
No
Q4
Q4
nnnn