ATMEGA1284-PU Atmel, ATMEGA1284-PU Datasheet - Page 174
![IC MCU AVR 128K FLASH 40PDIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA1284-PU
Manufacturer Part Number
ATMEGA1284-PU
Description
IC MCU AVR 128K FLASH 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1284-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.4.1
8272A–AVR–01/10
Internal Clock Generation – The Baud Rate Generator
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 18-2
Figure 18-2. Clock Generation Logic, Block Diagram
Signal description:
operation.
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 18-1 on page 175
for calculating the UBRRn value for each mode of operation using an internally generated clock
source.
Note:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
f
BAUD
OSC
DDR_XCK
1. The baud rate is defined to be the transfer rate in bit per second (bps)
XCK
Pin
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
Baud rate (in bits per second, bps)
Down-Counter
Prescaling
contains equations for calculating the baud rate (in bits per second) and
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure 18-2 on page
osc
/(UBRRn+1)). The Transmitter divides the
/4
/2
DDR_XCK
174.
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
174
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