DSPIC33FJ12MC202-I/SS Microchip Technology, DSPIC33FJ12MC202-I/SS Datasheet - Page 3
![IC DSPIC MCU/DSP 12K 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
DSPIC33FJ12MC202-I/SS
Manufacturer Part Number
DSPIC33FJ12MC202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ12MC202-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
UART
PWM
PWM
CPU
ADC
QEI
QEI
QEI
SPI
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY (CONTINUED)
Accumulation
Accumulation
Consumption
Debug Mode
DOZE Mode
Timer Gated
Timer Gated
Addressing
Generation
Instruction
Character
Interrupts
FRMDLY
Feature
in Sleep
Current
Break
10-bit
EXCH
Mode
Mode
Slave
Mode
—
—
Number
Item
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
With the I
interrupt input functions (if any) associated with SCL
and SDA pins do not reflect the actual digital logic levels
on the pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Signifi-
cant bits (LSbs) of the address are the same as the 7-bit
reserved addresses.
After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
The EXCH instruction does not execute correctly.
PTMR does not keep counting down after halting code
execution in Debug mode.
The Motor Control PWM module generates more inter-
rupts than expected when DOZE mode is used and the
output postscaler value is different than 1:1.
The QEI module does not generate an interrupt in a par-
ticular overflow condition.
The UART module will not generate back-to-back Break
characters.
When Timer Gated Accumulation is enabled, the QEI
does not generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an
external signal is applied, the POSCNT increments and
generates an interrupt after a match with MAXCNT.
The SPI communication in Framed mode does not func-
tion correctly if the Slave SPI frame delay bit (FRMDLY)
is set to ‘1’.
If the ADC module is in an enabled state when the
device enters Sleep Mode, the power-down current
(I
specifications.
PD
) of the device may exceed the device data sheet
2
C module enabled, the port bits and external
Issue Summary
A2 A3 A4 A5
X
X
X
X
X
X
X
X
X
X
X
X
DS80461E-page 3
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X