DSPIC33FJ12MC202-I/SS Microchip Technology, DSPIC33FJ12MC202-I/SS Datasheet - Page 45
![IC DSPIC MCU/DSP 12K 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
DSPIC33FJ12MC202-I/SS
Manufacturer Part Number
DSPIC33FJ12MC202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ12MC202-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 45 of 288
- Download datasheet (5Mb)
TABLE 4-23:
TABLE 4-24:
TABLE 4-25:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
Legend:
File Name
File Name
File Name
1:
2:
1:
Addr
0740
0742
0744
0746
0748
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
0770
0772
0774
0760
0766
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
Bit 15
ROI
IC8MD
Bit 15
Bit 15
—
—
—
WR
—
—
—
IOPUWR
Bit 14
IC7MD
Bit 14
WREN
—
—
Bit 14
—
—
—
COSC<2:0>
DOZE<2:0>
Bit 13
Bit 13
T3MD
WRERR
—
—
—
Bit 13
—
—
—
Bit 12
Bit 12
T2MD
—
—
—
—
—
Bit 12
—
—
DOZEN
Bit 11
T1MD
Bit 11
—
—
—
—
—
—
Bit 11
—
—
QEIMD
Bit 10
Bit 10
—
—
—
—
—
Bit 10
—
—
FRCDIV<2:0>
NOSC<2:0>
PWM1MD
IC2MD
Bit 9
Bit 9
CM
—
—
—
Bit 9
—
—
VREGS
Bit 8
IC1MD
Bit 8
—
—
—
Bit 8
—
—
CLKLOCK IOLOCK
EXTR
I2C1MD
Bit 7
PLLPOST<1:0>
Bit 7
—
—
—
Bit 7
—
Bit 6
SWR
—
Bit 6
ERASE
—
—
—
Bit 6
SWDTEN
LOCK
Bit 5
U1MD
—
Bit 5
—
—
Bit 5
—
PLLDIV<8:0>
WDTO
PWM2MD
Bit 4
—
Bit 4
Bit 4
—
—
NVMKEY<7:0>
—
SLEEP
Bit 3
SPI1MD
CF
Bit 3
Bit 3
—
—
TUN<5:0>
PLLPRE<4:0>
Bit 2
IDLE
—
Bit 2
Bit 2
—
—
—
NVMOP<3:0>
LPOSCEN
Bit 1
BOR
OC2MD
Bit 1
Bit 1
—
—
OSWEN
AD1MD
OC1MD
Bit 0
POR
Bit 0
Bit 0
—
Resets
xxxx
0300
3040
0030
0000
Resets
Resets
0000
0000
0000
0000
0000
All
All
All
(1)
(2)
(1)
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