PIC16C765T-I/PT Microchip Technology, PIC16C765T-I/PT Datasheet - Page 22

• Manufacturer Part Number: PIC16C765T-I/PT
• Description: IC MCU OTP 8KX14 USB 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C765T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SCI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.35 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 4.35 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C745/765
4.2.2.1
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 4-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
DS41124C-page 22
bit7
bit 7:
bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-
R/W-0
IRP
STATUS REGISTER
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
Preliminary
R/W-x
Z
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended that only BCF, BSF, SWAPF and
MOVWF instructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, C or DC bits
in the STATUS register. For other instructions which do
not affect status bits, see the "Instruction Set Sum-
mary."
R/W-x
Note 1: The C and DC bits operate as borrow and
DC
digit borrow bits, respectively, in subtrac-
tion. See the SUBLW and SUBWF instruc-
tions for examples.
R/W-x
(1)
C
(1)
bit0
(1)
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
2000 Microchip Technology Inc.
read as ‘0’