PIC16LF628-04I/SS Microchip Technology, PIC16LF628-04I/SS Datasheet - Page 70

• Manufacturer Part Number: PIC16LF628-04I/SS
• Description: IC MCU FLASH 2KX14 COMP 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF628-04I/SS

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16LF
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F62X
REGISTER 12-2:
DS40300C-page 68
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)
1 = Serial port enabled
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Synchronous mode - master:
Synchronous mode - slave:
CREN: Continuous Receive Enable bit
Asynchronous mode:
Synchronous mode:
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
Asynchronous mode 8-bit (RX9=0):
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be PARITY bit)
bit 7
Legend:
R = Readable bit
-n = Value at POR
R/W-0
SPEN
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as PARITY bit
Unused in this mode
Synchronous mode
Unused in this mode
Don’t care
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Unused in this mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
1 = Enables continuous receive
0 = Disables continuous receive
R/W-0
RX9
R/W-0
SREN
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
CREN
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
ADEN
FERR
 2003 Microchip Technology Inc.
R-0
x = Bit is unknown
OERR
R-0
RX9D
R-x
bit 0