ATMEGA16-16MQ Atmel, ATMEGA16-16MQ Datasheet - Page 209

MCU AVR 16K FLASH 16MHZ 44-QFN

ATMEGA16-16MQ

Manufacturer Part Number
ATMEGA16-16MQ
Description
MCU AVR 16K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA16-16MQ

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Differential Gain
Channels
2466T–AVR–07/10
Figure 103. ADC Timing Diagram, Auto Triggered Conversion
Figure 104. ADC Timing Diagram, Free Running Conversion
Table 81. ADC Conversion Time
When using differential gain channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
2
Conversion
Complete
3
One Conversion
Sample & Hold
11
4
Sample & Hold (Cycles
12
5
from Start of
Conversion)
6
1.5/2.5
13
13.5
1.5
2
7
One Conversion
ADC2
Next Conversion
1
MSB of Result
LSB of Result
8
. A conversion initiated by the user (that is,
2
MUX and REFS
Update
9
Conversion
10
3
Complete
Conversion Time (Cycles)
11
Sample & Hold
4
12
ADC2
ATmega16(L)
13/14
13
13.5
25
13
equal to half the ADC
MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
209

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