PIC16C782-E/SS Microchip Technology, PIC16C782-E/SS Datasheet - Page 22
![IC PIC MCU FLASH 8BIT 2K 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C782-E/SS
Manufacturer Part Number
PIC16C782-E/SS
Description
IC PIC MCU FLASH 8BIT 2K 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C781-ISO.pdf
(186 pages)
2.PIC16C781-ISO.pdf
(8 pages)
3.PIC16C781-ISO.pdf
(8 pages)
Specifications of PIC16C782-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x8b; D/A 1x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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PIC16C781/782
2.6
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
DS41171A-page 20
PIE1 Register
bit 7
bit 6
bit 5
bit 4
bit 3-1
bit 0
PERIPHERAL INTERRUPT ENABLE REGISTER (PIE1: 8Ch)
Legend:
R = Readable bit
- n = Value at POR
bit7
LVDIE: Low Voltage Detect Interrupt Enable bit
1 = LVD interrupt is enabled
0 = LVD interrupt is disabled
ADIE: Analog-to-Digital Converter Interrupt Enable bit
1 = Enables the Analog-to-Digital Converter interrupt
0 = Disables the Analog-to-Digital Converter interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
Unimplemented: Read as '0'
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
LVDIE
R/W-0
ADIE
R/W-0
C2IE
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
C1IE
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt (see
Register 2-3).
—
U-0
—
2001 Microchip Technology Inc.
x = Bit is unknown
U-0
—
TMR1IE
R/W-0
bit0
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