ATMEGA644A-MUR Atmel, ATMEGA644A-MUR Datasheet - Page 314
![IC MCU AVR 64K FLASH 44VQFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA644A-MUR
Manufacturer Part Number
ATMEGA644A-MUR
Description
IC MCU AVR 64K FLASH 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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26.9.1
26.10 Programming via the JTAG Interface
26.10.1
8272A–AVR–01/10
Serial Programming Characteristics
Programming Specific JTAG Instructions
For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page
336.
Figure 26-12. Serial Programming Waveforms
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
164A/164PA/324A/324PA/644A/644PA/1284/1284P
SERIAL DATA OUTPUT
SERIAL CLOCK INPUT
SERIAL DATA INPUT
SAMPLE
(MOSI)
(MISO)
(SCK)
Figure 26-13 on page
MSB
MSB
315.
LSB
LSB
314
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