AT89LP6440-20PU Atmel, AT89LP6440-20PU Datasheet - Page 104
AT89LP6440-20PU
Manufacturer Part Number
AT89LP6440-20PU
Description
MCU 8051 64K FLASH ISP 40PDIP
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP6440-20MU.pdf
(194 pages)
Specifications of AT89LP6440-20PU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18. Two-Wire Serial Interface
104
AT89LP6440 - Preliminary
The Two-Wire Interface (TWI) is a bi-directional 2-wire serial communication standard. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised
of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs
connected to them. The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. The
serial data transfer is limited to 400Kbit/s in standard mode. Various communication configura-
tions can be designed using this bus.
of the devices connected to the bus can be master or slave.
The Two-Wire Interface on the AT89LP provides the following features:
Figure 18-1. Two-Wire Bus Configuration
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tristate their outputs, allowing the pull-up resistors to pull the line
high. Note that all AT89LP devices connected to the TWI bus must be powered in order to allow
any bus operation. The number of devices that can be connected to the bus is only limited by the
bus capacitance limit of 400 pF and the 7-bit slave address space.
• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Fully Programmable Slave Address with General Call Support
SDA
SCL
Device 1
Figure
18-1, both bus lines are connected to the positive supply voltage through
Device 2
Figure 18-1
Device 3
shows a typical 2-wire bus configuration. Any
........
Device n
V
CC
R1
3706A–MICRO–9/09
R2
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