PIC18F8310-E/PT Microchip Technology, PIC18F8310-E/PT Datasheet - Page 204
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PIC18F8310-E/PT
Manufacturer Part Number
PIC18F8310-E/PT
Description
IC PIC MCU FLASH 8KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
Specifications of PIC18F8310-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8310-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
17.4.7.1
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
DS39635C-page 204
Clock Arbitration
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place and BRG starts its count
01h
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure
DX – 1
17-18).
SCL allowed to transition high
03h
2010 Microchip Technology Inc.
02h
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