DSPIC30F3013T-20I/ML Microchip Technology, DSPIC30F3013T-20I/ML Datasheet - Page 23
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3013T-20I/ML
Manufacturer Part Number
DSPIC30F3013T-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(6 pages)
4.DSPIC30F2011-20IP.pdf
(26 pages)
5.DSPIC30F3012-20ISO.pdf
(14 pages)
6.DSPIC30F3012-20ISO.pdf
(20 pages)
Specifications of DSPIC30F3013T-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20IP PDF datasheet #4
- DSPIC30F3012-20ISO PDF datasheet #5
- DSPIC30F3012-20ISO PDF datasheet #6
- Current page: 23 of 210
- Download datasheet (3Mb)
2.4
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The DSP engine also has the capability to perform
inherent
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow
architecture, therefore, concurrent operation of the
DSP engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction
(e.g., ED, EDAC). See
TABLE 2-2:
© 2010 Microchip Technology Inc.
Instruction
MOVSAC
MPY.N
EDAC
CLR
MAC
MAC
MPY
MSC
ED
DSP Engine
accumulator-to-accumulator
DSP INSTRUCTION
SUMMARY
No change in A
A = A + (x – y)
A = A + (x * y)
A = A – x • y
A = (x – y)
Operation
Algebraic
A = A + x
A = – x • y
A = x • y
Table
A = 0
2-2.
2
2
2
dsPIC30F2011/2012/3012/3013
ACC WB?
operations,
Yes
Yes
Yes
Yes
No
No
No
No
No
The DSP engine has several options selected through
various bits in the CPU Core Configuration register
(CORCON), which are:
1.
2.
3.
4.
5.
6.
7.
A block diagram of the DSP engine is shown in
Figure
Note:
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for ACCA (SATA).
Automatic saturation on/off for ACCB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator
(ACCSAT).
2-2.
For CORCON layout, see
Saturation
mode
DS70139G-page 23
Table
selection
3-3.
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