PIC18LF2221-I/SS Microchip Technology, PIC18LF2221-I/SS Datasheet - Page 319
![IC PIC MCU FLASH 2KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2221-I/SS
Manufacturer Part Number
PIC18LF2221-I/SS
Description
IC PIC MCU FLASH 2KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/SS
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2221-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18LF2221-IML PDF datasheet #5
- Current page: 319 of 394
- Download datasheet (7Mb)
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description
Words:
Cycles:
Example:
© 2005 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
operation
Decode
PC
PCLATH =
PCLATU =
W
PC
TOS
PCLATH =
PCLATU =
W
Q1
No
=
=
=
=
=
operation
Subroutine Call Using WREG
CALLW
None
(PC + 2)
(W)
(PCLATH)
(PCLATU)
None
First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a
new next instruction is fetched.
Unlike
update W, Status or BSR.
1
2
HERE
WREG
Read
0000
Q2
No
address (HERE)
10h
00h
06h
001006h
address (HERE + 2)
10h
00h
06h
CALL
PCL,
CALLW
TOS,
0000
PUSH PC to
, there is no option to
PCH,
PCU
operation
NOP
stack
Q3
No
instruction while the
0001
Advance Information
operation
operation
Q4
No
No
0100
MOVSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (destin.)
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
PIC18F4321 FAMILY
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
REG2
FSR2
Contents
of 85h
REG2
Q1
source addr
No dummy
Determine
operation
Move Indexed to f
MOVSF [z
0
0
((FSR2) + z
None
The contents of the source register are
moved to destination register ‘f
actual address of the source register is
determined by adding the 7-bit literal
offset ‘z
FSR2. The address of the destination
register is specified by the 12-bit literal
‘f
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h.
2
2
MOVSF
d
’ in the second word. Both addresses
read
1110
1111
Q2
No
=
=
=
=
=
=
z
f
d
s
s
4095
127
’ in the first word to the value of
80h
33h
11h
80h
33h
33h
[05h], REG2
s
s
1011
ffff
], f
)
source addr
Determine
operation
d
f
Q3
No
d
DS39689A-page 317
0zzz
ffff
source reg
register ‘f’
(dest)
Read
Write
d
Q4
zzzz
ffff
’. The
d
s
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