PIC18F66J10-I/PT Microchip Technology, PIC18F66J10-I/PT Datasheet - Page 116

IC PIC MCU FLASH 32KX16 64TQFP

PIC18F66J10-I/PT

Manufacturer Part Number
PIC18F66J10-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F66J10-I/PT

Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
50
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
A/d Bit Size
10 bit
A/d Channels Available
11
Height
1 mm
Length
10 mm
Supply Voltage (max)
2.7 V, 3.6 V
Supply Voltage (min)
2 V, 2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F66J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC18F66J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F87J10 FAMILY
10.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
REGISTER 10-4:
DS39663F-page 114
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
PSPIF
PIR Registers
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RC1IF: EUSART1 Receive Interrupt Flag bit
1 = The EUSART1 receive buffer, RCREGx, is full (cleared when RCREGx is read)
0 = The EUSART1 receive buffer is empty
TX1IF: EUSART1 Transmit Interrupt Flag bit
1 = The EUSART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)
0 = The EUSART1 transmit buffer is full
SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: ECCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
W = Writable bit
‘1’ = Bit is set
RC1IF
R-0
TX1IF
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSP1IF
R/W-0
Note 1: Interrupt flag bits are set when an interrupt
2: User
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
CCP1IF
R/W-0
software
© 2009 Microchip Technology Inc.
x = Bit is unknown
TMR2IF
R/W-0
should
ensure
TMR1IF
R/W-0
bit 0
the

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