PIC16LC72A-04I/ML Microchip Technology, PIC16LC72A-04I/ML Datasheet - Page 10
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PIC16LC72A-04I/ML
Manufacturer Part Number
PIC16LC72A-04I/ML
Description
IC MCU OTP 2KX14 A/D PWM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC72A-04I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16LC72A04I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LC72A-04I/ML
Manufacturer:
Microchip Technology
Quantity:
135
PIC16C62B/72A
TABLE 2-1
DS35008B-page 10
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,
Note 1: These registers can be addressed from either bank.
80h
81h
82h
83h
84h
85h
86h
87h
88h-89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-91h
92h
93h
94h
95h-9Eh
9Fh
Addr
Bank 1
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
Shaded locations are unimplemented, read as ’0’.
are transferred to the upper byte of the program counter.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
Name
(1)
(1)
(1)
—
—
—
—
(1)
(1,2)
(1)
(3)
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
RBPU
IRP
Bit 7
SMP
GIE
—
—
—
—
—
(5)
INTEDG
ADIE
RP1
Bit 6
PEIE
CKE
—
—
—
—
(5)
(3)
PORTA Data Direction Register
T0CS
Bit 5
T0IE
2
RP0
D/A
C mode) Address Register
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Preliminary
T0SE
INTE
Bit 4
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
S
CCP1IE
PCFG2
Bit 2
T0IF
R/W
PS2
—
Z
TMR2IE
PCFG1
Bit 1
INTF
POR
PS1
DC
UA
1999 Microchip Technology Inc.
TMR1IE
PCFG0
Bit 0
RBIF
BOR
PS0
BF
C
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
other resets
Value on all
---- -000
(4)
—
—
—
—