PIC16F88-E/P Microchip Technology, PIC16F88-E/P Datasheet - Page 126
PIC16F88-E/P
Manufacturer Part Number
PIC16F88-E/P
Description
IC MCU FLASH 4KX14 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F87-IP.pdf
(228 pages)
5.PIC16F87-IP.pdf
(8 pages)
6.PIC16F87-IP.pdf
(4 pages)
7.PIC16F87-IP.pdf
(8 pages)
Specifications of PIC16F88-E/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- PIC16F87-IP PDF datasheet #7
- Current page: 126 of 228
- Download datasheet (5Mb)
PIC16F87/88
FIGURE 13-3:
13.6
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2 register) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE2 register) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS30487C-page 124
Comparator Interrupts
Set CMIF bit
To Data Bus
COMPARATOR OUTPUT BLOCK DIAGRAM
From other Comparator
RD_CMCON
Q
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
Note:
Q
EN
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
D
CL
EN
D
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2
register) interrupt flag may not get set.
RESET
Q1
MULTIPLEX
Port Pins
2005 Microchip Technology Inc.
Q3 * RD_CMCON
CnINV
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