PIC18F24J50-I/SP Microchip Technology, PIC18F24J50-I/SP Datasheet - Page 315

• Manufacturer Part Number: PIC18F24J50-I/SP
• Description: IC PIC MCU FLASH 16K 2V 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24J50-I/SP

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 22
• Ram Memory Size: 3776Byte
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, MA180024, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 18-33:
FIGURE 18-34:
© 2009 Microchip Technology Inc.
After the SDAx pin has been deasserted and
allowed to float high, SDAx is sampled low after
the BRG has timed out.
After the SCLx pin is deasserted, SCLx is
sampled low before SDAx goes high.
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
SDAx
SCLx
PEN
BCLxIF
P
SSPxIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDAx asserted low
Assert SDAx
T
BRG
T
BRG
T
BRG
T
BRG
PIC18F46J50 FAMILY
The Stop condition begins with SDAx asserted low.
When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
the BRG is loaded with SSPxADD<6:0> and counts
down to 0. After the BRG times out, SDAx is sampled. If
SDAx is sampled low, a bus collision has occurred. This
is due to another master attempting to drive a data ‘0’
(Figure 18-33). If the SCLx pin is sampled low before
SDAx is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data ‘0’ (Figure 18-34).
SCLx goes low before SDAx goes high,
set BCLxIF
T
BRG
T
BRG
SDAx sampled
low after T
set BCLxIF
‘0’
‘0’
DS39931C-page 315
‘0’
‘0’
BRG
,