PIC18F2410-E/SP Microchip Technology, PIC18F2410-E/SP Datasheet - Page 214

• Manufacturer Part Number: PIC18F2410-E/SP
• Description: IC MCU FLASH 8KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2410-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC18F2X1X/4X1X
The analog reference voltage is software selectable
to either the device’s positive and negative supply
voltage (V
RA3/AN3/V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 18-1:
DS39636D-page 216
Note 1:
DD
REF
2:
and V
+ and RA2/AN2/V
Converter
Channels AN5 through AN7 are not available on 28-pin devices.
I/O pins have diode protection to V
10-bit
A/D
Reference
SS
Voltage
A/D BLOCK DIAGRAM
), or the voltage level on the
REF
-/CV
V
V
REF
REF
REF
+
-
(Input Voltage)
VCFG1:VCFG0
pins.
V
AIN
DD
and V
X
X
1
0
0
1
X
X
V
SS
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can
be configured as an analog input, or as a digital I/O.
The ADRESH and ADRESL registers contain the
result of the A/D conversion. When the A/D
conversion is complete, the result is loaded into the
ADRESH:ADRESL register pair, the GO/DONE bit
(ADCON0 register) is cleared and A/D Interrupt Flag
bit ADIF is set. The block diagram of the A/D module
is shown in Figure 18-1.
.
V
SS
CHS3:CHS0
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2009 Microchip Technology Inc.
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
(1)
(1)
(1)