PIC16C781-E/SO Microchip Technology, PIC16C781-E/SO Datasheet - Page 101

• Manufacturer Part Number: PIC16C781-E/SO
• Description: IC MCU OTP 1KX14 W/AD 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C781-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

13.0
The Programmable Switch Mode Controller module
provides all the necessary features to implement a
pulsed feedback control system. The PSMC generates
a pulse output based on its analog feedback.
Feedback from the comparator is programmable,
allowing:
• Single or dual channel feedback
• Programmable reference voltage selection
• Programmable polarity
The pulse output of the PSMC is also programmable,
featuring either Pulse Width (PWM) or Pulse Skip
(PSM) Modulation. In PSM, a fixed duty cycle is gener-
ated or skipped, based on feedback. In PWM a feed-
back controlled pulse width is generated. In addition,
the output configuration of the PSMC is programmable,
enabling the following features:
• A single output
• A single output plus a slope compensation output
• Dual alternating outputs
FIGURE 13-1:
2001 Microchip Technology Inc.
SMCCL1
SMCCL0
F
OSC
PROGRAMMABLE SWITCH
MODE CONTROLLER (PSMC)
MAXDC<1:0>
MINDC<1:0>
C1POL
C2POL
Comparator Module
1:1
C1
C2
S1
3
S0
1:2
2
PSMC MODULE IN SINGLE OUTPUT PWM MODE (SIMPLIFIED BLOCK
DIAGRAM)
PSMC
CLK
1:4 1:8
1
2
2
0
Controller
4-bit Counter
PSMC
4
Switch
Cycle
New
Max
C1OUT
SMCCS
C2OUT
DC
SC
DC = Duty Cycle
EXAMPLE
New Cycle
Max D/C
SC Switch
C1OUT
RB6/C1/
PSMC1A
RB7/C2/
PSMC1B/T1G
Preliminary
ASSUMES S1APOL=0
All pulse start and duty cycle limit timing features of the
PSMC are derived from the internal CPU clock.
Block diagrams for the PSMC are shown in Figure 13-1
through Figure 13-3.
13.1
In the PWM mode, the PSMC (shown in Figure 13-1
and Figure 13-2) is a timer-driven set/RESET pulse
generator. Pulses are initiated by the internal counter
chain. Following the completion of the programmable
minimum duty cycle, the output pulse is terminated by
either a high to low transition on the comparator output,
or by the programmable maximum duty cycle (see
Table 13-1 and Table 13-2). The resulting output is a
variable duty cycle pulse with:
• Programmable frequency
• Feedback specified duty cycle
• Programmable minimum duty cycle including 0%
• Programmable maximum duty cycle
SCEN
Min DC
S1APOL
Pulse Width Modulation (PWM)
SMCCS=0
Dominant
S
R
HIGH IMPEDANCE
Set
PIC16C781/782
Q
Period
SCEN=1
SMCON=1 SMCOM=0
V
DD
N
PWM/PSM=1
RB7/C2/PSMC1B/T1G
RB6/C1/PSMC1A
DS41171A-page 99
HIGH IMPEDANCE