ATMEGA168A-AU Atmel, ATMEGA168A-AU Datasheet - Page 232
![IC MCU AVR 16K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA168A-AU
Manufacturer Part Number
ATMEGA168A-AU
Description
IC MCU AVR 16K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA168A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA168x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA168A-AU
Manufacturer:
ATMEL
Quantity:
464
Part Number:
ATMEGA168A-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8271C–AVR–08/10
Figure 21-13. Data Transfer in Master Receiver Mode
A START condition is sent by writing the following value to TWCR:
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI
will then test the 2-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-
ware, and the status code in TWSR will be 0x08 (See
SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in
Flag is set high by hardware. This scheme is repeated until the last byte has been received.
After the last byte has been received, the MR should inform the ST by sending a NACK after the
last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
TWCR
value
TWCR
value
TWCR
value
TWCR
value
SDA
SCL
Table
TWINT
TWINT
TWINT
TWINT
1
1
1
1
21-3. Received data can be read from the TWDR Register when the TWINT
Device 1
RECEIVER
MASTER
TWEA
TWEA
TWEA
TWEA
X
X
X
X
TRANSMITTER
Device 2
SLAVE
TWSTA
TWSTA
TWSTA
TWSTA
1
0
0
1
Device 3
TWSTO
TWSTO
TWSTO
TWSTO
0
0
1
0
........
Table
TWWC
TWWC
TWWC
TWWC
Device n
X
X
X
X
21-2). In order to enter MR mode,
V
CC
TWEN
TWEN
TWEN
TWEN
1
1
1
1
R1
R2
–
0
–
0
–
0
–
0
TWIE
TWIE
TWIE
TWIE
X
X
X
X
232
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