PIC18LF25K22-I/SP Microchip Technology, PIC18LF25K22-I/SP Datasheet - Page 222
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PIC18LF25K22-I/SP
Manufacturer Part Number
PIC18LF25K22-I/SP
Description
MCU 8BIT 32KB FLASH 3.6V 28SDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F26J13-ISS.pdf
(496 pages)
2.PIC18F25K22T-ISS.pdf
(10 pages)
3.PIC18F25K22-ISP.pdf
(492 pages)
Specifications of PIC18LF25K22-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC18(L)F2X/4XK22
15.4.9
The 9th SCLx pulse for any transferred byte in I
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDAx line low. The transmitter must release con-
trol of the line during this time to shift in the response.
The Acknowledge (ACK) is an active-low signal, pull-
ing the SDAx line low indicated to the transmitter that
the device has received the transmitted data and is
ready to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2
register is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPxCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT
register or the SSPxOV bit of the SSPxCON1 register
are set when a byte is received.
When the module is addressed, after the 8th falling
edge of SCLx on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus.
The ACKTIM Status bit is only active when the AHEN
bit or DHEN bit is enabled.
DS41412B-page 222
ACKNOWLEDGE SEQUENCE
2
C is
Preliminary
15.5
The MSSPx Slave mode operates in one of four
modes selected in the SSPxM bits of SSPxCON1
register. The modes can be divided into 7-bit and 10-bit
Addressing mode. 10-bit Addressing modes operate
the same as 7-bit with some additional overhead for
handling the larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
15.5.1
The SSPxADD register (Register 15-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes Idle and no indication is given to the
software that anything happened.
The SSPx Mask register (Register 15-5) affects the
address matching process.
“SSPx Mask Register” for more information.
15.5.1.1
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
15.5.1.2
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCLx is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPxADD. Even if there is not an address match;
SSPxIF and UA are set, and SCLx is held low until
SSPxADD is updated to receive a high byte again.
When SSPxADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing
communication. A transmission can be initiated by
issuing a Restart once the slave is addressed, and
clocking in the high address with the R/W bit set. The
slave hardware will then acknowledge the read
request and prepare to clock out data. This is only
valid for a slave after it has received a complete high
and low address byte match.
I
SLAVE MODE ADDRESSES
2
C
I
I
2
2
C Slave 7-bit Addressing Mode
C Slave 10-bit Addressing Mode
SLAVE MODE OPERATION
2010 Microchip Technology Inc.
See
Section 15.5.9
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