AT32UC3L064-D3UR Atmel, AT32UC3L064-D3UR Datasheet - Page 257
AT32UC3L064-D3UR
Manufacturer Part Number
AT32UC3L064-D3UR
Description
MCU AVR32 64KB FLASH 48TLLGA
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3L-EK.pdf
(858 pages)
Specifications of AT32UC3L064-D3UR
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TLLGA
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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14.6.3
Name:
Access Type:
Offset:
Reset Value:
• CLKRDY: Clock Ready
• CLKBUSY: Clock Busy
• READY: AST Ready
• BUSY: AST Busy
• PERn: Periodic n
• ALARMn: Alarm n
• OVF: Overflow
32099F–11/2010
31
23
15
7
-
-
-
-
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.CLKBUSY bit has a 1-to-0 transition.
0: The clock is ready and can be changed.
1: CLOCK.CEN has been written and the clock is busy.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.BUSY bit has a 1-to-0 transition.
0: The AST accepts writes to CR, CV, SCR, WER, EVE, EVD, ARn, PIRn, and DTR.
1: The AST is busy and will discard writes to CR, CV, SCR, WER, EVE, EVD, ARn, PIRn, and DTR.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the selected bit in the prescaler has a 0-to-1 transition.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the counter reaches the selected alarm value.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overflow has occurred.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x08
0x00000000
CLKRDY
29
21
13
5
-
-
-
CLKBUSY
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
AT32UC3L016/32/64
ALARM1
READY
PER1
25
17
9
1
-
ALARM0
BUSY
PER0
OVF
24
16
8
0
257
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