PIC16F628A-I/ML Microchip Technology, PIC16F628A-I/ML Datasheet - Page 175

• Manufacturer Part Number: PIC16F628A-I/ML
• Description: IC MCU FLASH 2KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F628A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Q
Q-Clock ............................................................................... 59
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator ....................................................................... 99
RC Oscillator Mode
Reader Response ............................................................. 170
Registers
Reset................................................................................... 99
RETFIE Instruction............................................................ 124
RETLW Instruction ............................................................ 125
RETURN Instruction ......................................................... 125
Revision History ................................................................ 167
RLF Instruction.................................................................. 125
RRF Instruction ................................................................. 126
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Production (SQTP) Devices ... 7
SLEEP Instruction ............................................................. 126
Software Simulator (MPLAB SIM)..................................... 130
Special Event Trigger. See Compare
Special Features of the CPU .............................................. 95
Special Function Registers ................................................. 18
Status Register ................................................................... 22
SUBLW Instruction............................................................ 126
SUBWF Instruction ........................................................... 127
SWAPF Instruction............................................................ 127
T
T1CKPS0 bit ....................................................................... 48
T1CKPS1 bit ....................................................................... 48
T1CON Register ................................................................. 48
T1OSCEN bit ...................................................................... 48
T1SYNC bit ......................................................................... 48
T2CKPS0 bit ....................................................................... 53
T2CKPS1 bit ....................................................................... 53
T2CON Register ................................................................. 53
Timer0
© 2007 Microchip Technology Inc.
Duty Cycle................................................................... 59
Example Frequencies/Resolutions ............................. 59
Period.......................................................................... 58
Set-Up for PWM Operation ......................................... 59
TMR2 to PR2 Match ................................................... 58
Block Diagram............................................................. 99
CCP1CON (CCP Operation)....................................... 55
CMCON (Comparator Configuration).......................... 61
CONFIG (Configuration Word).................................... 96
EECON1 (EEPROM Control Register 1) .................... 90
INTCON (Interrupt Control)......................................... 24
Maps
OPTION_REG (Option) .............................................. 23
PCON (Power Control) ............................................... 27
PIE1 (Peripheral Interrupt Enable 1)........................... 25
PIR1 (Peripheral Interrupt Register 1) ........................ 26
Status.......................................................................... 22
T1CON Timer1 Control).............................................. 48
T2CON Timer2 Control).............................................. 53
Block Diagrams
External Clock Input.................................................... 45
Interrupt....................................................................... 45
PIC16F627A ................................................. 16, 17
PIC16F628A ................................................. 16, 17
Timer0/WDT ....................................................... 46
PIC16F627A/628A/648A
Timer1
Timer2
Timing Diagrams
Timing Diagrams and Specifications ................................ 142
TMR0 Interrupt.................................................................. 108
TMR1CS bit ........................................................................ 48
TMR1ON bit........................................................................ 48
TMR2ON bit........................................................................ 53
TOUTPS0 bit ...................................................................... 53
TOUTPS1 bit ...................................................................... 53
TOUTPS2 bit ...................................................................... 53
TOUTPS3 bit ...................................................................... 53
TRIS Instruction ................................................................ 127
TRISA ................................................................................. 31
TRISB ................................................................................. 36
U
Universal Synchronous Asynchronous Receiver
USART
Prescaler .................................................................... 46
Switching Prescaler Assignment ................................ 47
Timer0 Module............................................................ 45
Asynchronous Counter Mode ..................................... 50
Capacitor Selection .................................................... 51
External Clock Input ................................................... 49
External Clock Input Timing........................................ 50
Oscillator..................................................................... 51
Prescaler .............................................................. 49, 51
Resetting Timer1 ........................................................ 51
Resetting Timer1 Registers ........................................ 51
Special Event Trigger (CCP) ...................................... 57
Synchronized Counter Mode ...................................... 49
Timer Mode ................................................................ 49
TMR1H ....................................................................... 50
TMR1L........................................................................ 50
Block Diagram ............................................................ 52
Postscaler................................................................... 52
PR2 register................................................................ 52
Prescaler .............................................................. 52, 59
Timer2 Module............................................................ 52
TMR2 output ............................................................... 52
TMR2 to PR2 Match Interrupt..................................... 58
Timer0 ...................................................................... 145
Timer1 ...................................................................... 145
USART
USART Asynchronous Master Transmission ............. 78
USART Asynchronous Reception .............................. 81
USART Synchronous Reception ................................ 87
USART Synchronous Transmission ........................... 85
Asynchronous Receiver
Asynchronous Receiver Mode
Asynchronous Mode................................................... 77
Asynchronous Receiver.............................................. 80
Asynchronous Reception............................................ 82
Asynchronous Transmission ...................................... 78
Asynchronous Transmitter.......................................... 77
Baud Rate Generator (BRG) ...................................... 73
Block Diagrams
BRGH bit .................................................................... 73
Transmitter (USART)................................................. 71
Asynchronous Receiver...................................... 81
Setting Up Reception.......................................... 83
Address Detect ................................................... 83
Block Diagram .................................................... 83
Transmit.............................................................. 78
USART Receive ................................................. 80
DS40044F-page 173