PIC18F67J11T-I/PT Microchip Technology, PIC18F67J11T-I/PT Datasheet - Page 285
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J11T-I/PT
Manufacturer Part Number
PIC18F67J11T-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(4 pages)
4.PIC18F63J11-IPT.pdf
(36 pages)
5.PIC18F66J11-IPT.pdf
(4 pages)
6.PIC18F66J11-IPT.pdf
(4 pages)
7.PIC18F66J11-IPT.pdf
(20 pages)
8.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F67J11T-I/PT
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
3930 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
52
Ram Memory Size
3930Byte
Cpu Speed
48MHz
No. Of Timers
5
No. Of Pwm
RoHS Compliant
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 15 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F67J11T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J11T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- PIC18F63J11-IPT PDF datasheet #4
- PIC18F66J11-IPT PDF datasheet #5
- PIC18F66J11-IPT PDF datasheet #6
- PIC18F66J11-IPT PDF datasheet #7
- PIC18F66J15-IPT PDF datasheet #8
- Current page: 285 of 400
- Download datasheet (7Mb)
23.2
For PIC18F87J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is selected
by a multiplexor, controlled by the WDTPS bits in Config-
uration Register 2H. Available periods range from about
4 ms to 135 seconds (2.25 minutes depending on
voltage, temperature and WDT postscaler). The WDT
and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 23-1:
REGISTER 23-9:
TABLE 23-3:
© 2006 Microchip Technology Inc.
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
WDTPS3:WDTPS0
Name
All Device Resets
INTRC Oscillator
Watchdog Timer (WDT)
SWDTEN
CLRWDT
bit 7-1
bit 0
Sleep
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Legend:
R = Readable bit
-n = Value at POR
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
U-0
—
Bit 6
Enable WDT
—
—
U-0
WDT Counter
—
Bit 5
—
—
128
INTRC Control
4
U-0
Bit 4
—
Preliminary
Programmable Postscaler
RI
—
W = Writable bit
‘1’ = Bit is set
1:1 to 1:32,768
Bit 3
U-0
—
TO
—
23.2.1
The WDTCON register (Register 23-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
Bit 2
U-0
PD
WDT
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
(1)
Bit 1
POR
PIC18F87J10
—
U-0
—
SWDTEN
Bit 0
BOR
x = Bit is unknown
U-0
—
DS39663D-page 283
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on page
R/W-0
50
50
bit 0
(1)
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