PIC18F25K22-I/SO Microchip Technology, PIC18F25K22-I/SO Datasheet - Page 3

• Manufacturer Part Number: PIC18F25K22-I/SO
• Description: MCU 8BIT 32KB FLASH 5.5V 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25K22-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: Voltage Reference
2. Module: HLVD
 2010 Microchip Technology Inc.
Note:
1.1
Work around
Select the desired fixed voltage reference buffer
as part of initialization.
Affected Silicon Revisions
1.2
Work around
None.
Affected Silicon Revisions
Although the HLVDIF flag will be set immediately
after enabling the HLVD circuit, the HLVD module
is not functional and should not be used.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
is 0x00 instead of 0x10.
unstable at cold temperature.
The default value of VREFCON0 after Reset
Internal voltage reference may become
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A3
A3
A3
X
X
X
A4
A4
A4
3. Module: Comparators
4. Module: HS Oscillator
5. Module: Clock Switching
PIC18(L)F25/45K22
The CxSYNC controls are inoperative. The
comparator output (Cx) always bypasses the
Timer1 synchronization latch.
Work around
None.
Affected Silicon Revisions
The HS oscillator may not start when V
than 3V, especially at high temperatures.
Work around
None.
Affected Silicon Revisions
5.1
Work around
Disable HFINTOSC stabilization time by setting
the HFOFST bit of the Configuration register 3H.
Affected Silicon Revisions
5.2
Work around
The IESO Configuration bit must also be set when
the FCMEN Configuration bit is set.
Affected Silicon Revisions
A2
A2
A2
A2
X
X
X
Switchover mode is selected, then code
execution will be delayed after waking from
Sleep by the start-up time of the HFINTOSC.
and the IESO Configuration bit is not set,
then a clock failure during Sleep will not be
detected.
When Clock Fail-Safe mode or Clock
When the FCMEN Configuration bit is set
A3
A3
A3
A3
X
X
X
A4
A4
A4
A4
X
DS80498B-page 3
DD
is less