ATTINY461A-XU Atmel, ATTINY461A-XU Datasheet - Page 123
ATTINY461A-XU
Manufacturer Part Number
ATTINY461A-XU
Description
IC MCU AVR 4K FLASH 20MHZ 20TSSP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY461A-XU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY461A-XU
Manufacturer:
Atmel
Quantity:
1 974
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13. USI – Universal Serial Interface
13.1
13.2
8197B–AVR–01/10
Features
Overview
•
•
•
•
•
•
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
refer to
tions are listed in the
Figure 13-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) is directly accessible via the data bus and contains the
incoming and outgoing data. The register has no buffering so the data must be read as quickly
as possible to ensure that no data is lost. The data register is a serial shift register where the
most significant bit is connected to one of two output pins depending of the wire mode configura-
tion. A transparent latch between the output of the data register and the output pin delays the
change of data output to the opposite clock edge of the data input sampling. The serial input is
always sampled from the Data Input (DI) pin, regardless of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Pinout ATtiny261A/461A/861A” on page
USIDR
USICR
USIDB
USISR
2
“Register Descriptions” on page
4-bit Counter
3
2
1
0
3
2
1
0
D Q
LE
[1]
TIM0 COMP
Figure 13-1
0
1
2. Device-specific I/O Register and bit loca-
130.
Two-wire Clock
Control Unit
For actual placement of I/O pins
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
123
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