PIC18F1320-E/P Microchip Technology, PIC18F1320-E/P Datasheet - Page 16
![IC MCU FLASH 4KX16 EEPROM 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC18F1320-E/P
Manufacturer Part Number
PIC18F1320-E/P
Description
IC MCU FLASH 4KX16 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
7.PIC18F1320-ISS.pdf
(36 pages)
8.PIC18F1220-EP.pdf
(310 pages)
Specifications of PIC18F1320-E/P
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP180 - DEVICE ADAPTER 18F1320 PDIP 18LDACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC18FX220/X320
3.4
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a Data Latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, loading EEDATA with the
data to be written and initiating a memory write by
appropriately configuring the EECON1 and EECON2
registers. A byte write automatically erases the location
and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort and this
must be done prior to initiating a write sequence.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h,
and then 0AAh, immediately prior to asserting the WR
bit in order for the write to occur. The write sequence is
initiated by setting the WR bit (EECON1<1> = 1). It is
strongly recommended that the WREN bit be set only
when absolutely necessary.
The write will begin on the falling edge of the 4th PGC
after the WR bit is set.
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-8:
DS39592F-page 16
PGC
PGD
4-Bit Command
Data EEPROM Programming
1
0
2
0
3
0
4
0
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
2
15 16
P5A
4-Bit Command
1
0
2
0
3
0
4
0
PGD = Input
P5
1
0
Data Payload
2
0
16-Bit
FIGURE 3-7:
15 16
0
0
P5A
4-Bit Command
1
0
2
0
3
No
0
4
0
Unlock Sequence
for Write to Occur
0AAh – EECON2
Delay P11 + P10
PROGRAM DATA FLOW
55h – EECON2
2010 Microchip Technology Inc.
Enable Write
Set Address
Start Write
Sequence
Set Data
Data EEPROM
Done?
Done
Start
Write Time
P11
Yes
P11
Data Payload
16-Bit
1
n
2
n