ATTINY261-20SU Atmel, ATTINY261-20SU Datasheet - Page 65

• Manufacturer Part Number: ATTINY261-20SU
• Description: IC MCU AVR 2K FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2588E–AVR–08/10
Table 10-4
shown in
Table 10-4.
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 10-5 on page
and
PA7/ADC6/AIN0/
PCINT7
0
0
0
0
0
0
0
PCINT7 • PCIE +
ADC6D
ADC6D
PCINT7
ADC6, AIN0
PA3/AREF/
PCINT3
0
0
0
0
0
0
0
PCINT3 •
PCIE
0
PCINT3
AREF
Overriding Signals for Alternate Functions in PA7:PA4
Overriding Signals for Alternate Functions in PA3:PA0
Table 10-5
PA2/ADC2/INT1/
USCK/SCL/PCINT2
0
0
USI_TWO_WIRE •
USIPOS
(USI_SCL_HOLD +
PORTB2) • DDB2 •
USIPOS
USI_TWO_WIRE •
DDRB2
0
USI_PTOE • USIPOS
PCINT2 • PCIE + INT1 +
ADC2D + USISIE •
USIPOS
ADC2D
USCK/SCL/INT1/ PCINT2
ADC2
relate the alternate functions of Port A to the overriding signals
61.
PA6/ADC5/AIN1/
PCINT6
0
0
0
0
0
0
0
PCINT6 • PCIE +
ADC5D
ADC5D
PCINT6
ADC5, AIN1
PA1/ADC1/DO/
PCINT1
0
0
0
0
USI_THREE_WI
RE • USIPOS
DO • USIPOS
0
PCINT1 • PCIE +
ADC1D
ADC1D
PCINT1
ADC1
PA5/ADC4/AIN2/
PCINT5
0
0
0
0
0
0
0
PCINT5 • PCIE +
ADC4D
ADC4D
PCINT5
ADC4, AIN2
PA0/ADC0/DI/SDA/
PCINT0
0
0
USI_TWO_WIRE •
USIPOS
(SDA + PORTB0) •
DDRB0 • USIPOS
USI_TWO_WIRE •
DDRB0 • USIPOS
0
0
PCINT0 • PCIE +
ADC0D + USISIE •
USIPOS
ADC0D
DI/SDA/PCINT0
ADC0
PA4/ADC3/ICP0/
PCINT4
0
0
0
0
0
0
0
PCINT4 • PCIE +
ADC3D
ADC3D
ICP0/PCINT4
ADC3
65