ATMEGA168PV-10PU Atmel, ATMEGA168PV-10PU Datasheet - Page 196
![MCU AVR 16K FLASH 10MHZ 28-PDIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATMEGA168PV-10PU
Manufacturer Part Number
ATMEGA168PV-10PU
Description
MCU AVR 16K FLASH 10MHZ 28-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA168PV-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
10MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (9Mb)
8025L–AVR–7/10
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 19-5.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 19-6.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 19-7.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
UCSZn2
UPMn1
0
0
1
1
0
0
0
0
1
1
1
1
UPMn Bits Settings
USBS Bit Settings
UCSZn Bits Settings
USBSn
0
1
UCSZn1
UPMn0
0
1
0
1
0
0
1
1
0
0
1
1
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Stop Bit(s)
1-bit
2-bit
UCSZn0
0
1
0
1
0
1
0
1
ATmega48P/88P/168P
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
196
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