ATMEGA48-20MU Atmel, ATMEGA48-20MU Datasheet - Page 35
![IC AVR MCU 4K 20MHZ 5V 32-QFN](/photos/12/32/123213/atmega48-20mu_sml.jpg)
ATMEGA48-20MU
Manufacturer Part Number
ATMEGA48-20MU
Description
IC AVR MCU 4K 20MHZ 5V 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48-20MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USART/Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
32MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA48-20MU
Manufacturer:
ATMEL
Quantity:
18 000
- Current page: 35 of 378
- Download datasheet (8Mb)
8.10
8.11
2545S–AVR–07/10
Timer/Counter Oscillator
System Clock Prescaler
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-
nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with
XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an
internal RC Oscillator is selected as system clock source. See
connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to
logic one. See
on selecting external clock as input instead of a 32 kHz crystal.
The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by
setting the
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clk
divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-
vious clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
CLKPR to zero.
“CLKPR – Clock Prescale Register” on page
“Asynchronous Operation of Timer/Counter2” on page 150
Table 8-14 on page
37.
I/O
36. This feature can be used to
ATmega48/88/168
, clk
Figure 8-2 on page 29
ADC
, clk
CPU
for further description
, and clk
for crystal
FLASH
are
35
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