32UC3L064-AUT Atmel, 32UC3L064-AUT Datasheet - Page 9
![IC MCU 64K FLASH 16K SRAM 48TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
32UC3L064-AUT
Manufacturer Part Number
32UC3L064-AUT
Description
IC MCU 64K FLASH 16K SRAM 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.ATAVRONE-PROBECBL.pdf
(16 pages)
Specifications of 32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Peripheral DMA Controller
The Atmel Peripheral DMA controller sets a
new standard for data transfer efficiency. If
the Peripheral DMA controller is not en-
abled, the maximum usable transfer rate on
the SPI module would be approximately 1
MBit/s, occupying the CPU with more than
50% load just moving data around. With the
Peripheral DMA controller this bottleneck is
removed and the AVR32 UC3 microcontroller
can achieve a transfer rate of 33 MBit/s on
SPI and USART with only a 15% load on the
CPU. The UC3 can even toggle the I/O pins
at 33 MHz.
A higher level interrupt will halt execution of a lower level interrupt routine. The lower level
interrupt routine will continue and finish after the higher level interrupt routine finishes.
A second interrupt at an interrupt level already being serviced, will pend until the first
interrupt routine finishes.
Interrupt Controller
The 32-bit AVR UC3 CPU includes a multi-level interrupt
controller. Four priority levels are supported where higher
level interrupts are prioritized and executed before low level
interrupts. All peripherals can be assigned any interrupt level
and the interrupt vector addresses can be changed without
stopping the CPU. Interrupt latencies are very fast, typically
11 clock cycles including saving the register file to the stack.
Medium-level
Medium-level
Medium-level
High-level
High-level
Low-level
Main
Main
Program Flow and Interrupt execution
Program Flow and Interrupt execution
1
1
1
2
2
1
1
HOLD
3
3
HOLD
HOLD
HOLD
www.atmel.com
3
3
2
2
1
1
Main
Main
2
2
1
1
Main
Main
page 8