PIC18LF1320-I/SOG Microchip Technology, PIC18LF1320-I/SOG Datasheet - Page 146
![IC PIC MCU FLASH 4KX16 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC18LF1320-I/SOG
Manufacturer Part Number
PIC18LF1320-I/SOG
Description
IC PIC MCU FLASH 4KX16 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
Specifications of PIC18LF1320-I/SOG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F1220-ISO PDF datasheet #2
- PIC18F1220-ISO PDF datasheet #3
- PIC18F1220-ISO PDF datasheet #4
- PIC18F1220-ISO PDF datasheet #5
- PIC18F1220-ISO PDF datasheet #6
- Current page: 146 of 308
- Download datasheet (5Mb)
PIC18F1220/1320
To set up an Asynchronous Transmission:
1.
2.
3.
4.
FIGURE 16-6:
TABLE 16-6:
DS39605F-page 144
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 16.2 “EUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
EUSART Receive Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
GIE/GIEH
CSRC
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after
the third word, causing the OERR (overrun) bit to be set.
SPEN
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
ASYNCHRONOUS RECEPTION
bit
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
bit 1
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
INT0IE
CREN
SYNC
SCKP
Bit 4
TXIF
TXIE
TXIP
Stop
bit
ADDEN
SENDB
BRG16
Word 1
RCREG
RBIE
Bit 3
Start
—
—
—
bit
bit 0
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
BRGH
FERR
Bit 2
—
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
INT0IF
OERR
TRMT
WUE
Bit 1
bit 7/8
Word 2
RCREG
Stop
bit
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
Start
bit
© 2007 Microchip Technology Inc.
0000 000x
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7/8
Stop
bit
0000 000u
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Value on
all other
Resets
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