PIC16LC771-I/P Microchip Technology, PIC16LC771-I/P Datasheet - Page 75
![IC MCU OTP 4KX14 A/D PWM 20DIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC16LC771-I/P
Manufacturer Part Number
PIC16LC771-I/P
Description
IC MCU OTP 4KX14 A/D PWM 20DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC771-I/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC771I/P
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9.1.5
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.1.6
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISB<1> must be set. When the SS pin is low,
transmission and reception are enabled and the
FIGURE 9-4:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
2002 Microchip Technology Inc.
SLAVE MODE
SLAVE SELECT
SYNCHRONIZATION
SLAVE SYNCHRONIZATION WAVEFORM
bit7
bit7
bit6
Advance Information
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desir-
able, depending on the application.
When the SPI module RESETS, the bit counter is
forced to 0. This can be done by either forcing the SS
pin to a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
Note 1: When the SPI module is in Slave mode
PIC16C717/770/771
2: If the SPI is used in Slave Mode with
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
RESET if the SS pin is set to V
CKE = ’1’, then SS pin control must be
enabled.
bit7
bit7
Next Q4 cycle
after Q2
DS41120B-page 73
bit0
bit0
DD
.
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