PIC16F627A-I/SS Microchip Technology, PIC16F627A-I/SS Datasheet - Page 3

• Manufacturer Part Number: PIC16F627A-I/SS
• Description: IC MCU FLASH 1KX14 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627A-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPI3DBF648 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164018 - MODULE SKT PROMATEII 20SSOP
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4. Module: USART Control
1.
© 2008 Microchip Technology Inc.
USART
RB2/TX/CK differs from the data sheet. Figure
5-9 and Figure 5-10 indicate that the USART
circuit overrides the output drivers via the
Peripheral OE signal. In fact, the Peripheral OE
signal forces the TRISB<2:1> to an output
(Reset) state (see Figure 1). Subsequently, the
TRISB<2:1> must be set or configured to
receive data.
Work around
In Asynchronous mode, when transmit is enabled
(TXEN = 1 and SPEN = 1), the TRISB<2> latch is
cleared to ‘0’ by the USART peripheral circuitry.
When disabling transmit (TXEN = 0), the
TRISB<2> bit should be set to ‘1’ to configure the
RB2/TX/CK pin as an input.
In Synchronous mode, when changing from
transmit to receive, clear the TXEN bit first, then set
TRISB<1> to ‘1’ to configure the RB1/RX/DT pin as
an input before setting SREN or CREN to receive.
When disabling the USART (SPEN = 0), TRIS<2:1>
should be reconfigured for input or output as
required by the application.
control
of
the
RB1/RX/DT
and
PIC16F627A/628A/648A
FIGURE 1:
WR PORTB
WR TRISB
Peripheral OE
RD TRISB
RD PORTB
RBPU
SPEN
USART Output
Data Bus
Note
USART Input
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
(1)
BLOCK DIAGRAM OF RBI, RB2
TRIS Latch
Data Latch
D
D
CK
CK
R
Q
Q
Schmitt
Q
Trigger
Q
Q
EN
1
0
D
TTL
Input
Buffer
DS80151N-page 3
V
P
DD
V
V
Weak
Pull-up
DD
SS