ATTINY2313V-10SU Atmel, ATTINY2313V-10SU Datasheet - Page 29

• Manufacturer Part Number: ATTINY2313V-10SU
• Description: IC MCU AVR 2K FLASH 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313V-10SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 10MHz
• Interface Type: SPI/USART/USI
• Total Internal Ram Size: 128Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Package: 20SOIC
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Processor Series: ATTINY2x
• Core: AVR8
• Data Ram Size: 128 B
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR Tiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

2543L–AVR–08/10
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3:0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 12 on page
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 12. Clock Prescaler Select
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKPS2
29.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
256
16
32
64
1
2
4
8
29