PIC18F44J10-I/PT Microchip Technology, PIC18F44J10-I/PT Datasheet
PIC18F44J10-I/PT
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PIC18F44J10-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F45J10 Family 28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS39682C ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F24J10 16K 8192 PIC18F25J10 32K 16384 PIC18F44J10 16K 8192 PIC18F45J10 32K 16384 © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Peripheral Highlights: • High-current sink/source 25 mA/25 mA (PORTB and PORTC) • Three programmable external interrupts • Four input change interrupts • ...
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... OSC2/CLKO * Pin feature is dependent on device configuration. DS39682C-page REF 5 24 REF + CAP REF + 2 20 REF /V 3 PIC18F24J10 CAP PIC18F25J10 Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RC7/RX/DT © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F45J10 FAMILY VREF REF 5 36 CAP PIC18F44J10 PIC18F45J10 Preliminary RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/T0CKI/C1OUT RB4/KBI0/AN11 RB3/AN9/CCP2* RB2/INT2/AN8 RB1/INT1/AN10 RB0/INT0/FLT0/AN12 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO1 RC4/SDI1/SDA1 RD3/PSP3/SS2 RD2/PSP2/SDO2 OSC2/CLKO OSC1/CLKI RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS1/C2OUT V /V DDCORE CAP ...
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... PIC18F45J10 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 RB3/AN9/CCP2* * Pin feature is dependent on device configuration. DS39682C-page RC0/T1OSO/T1CKI 2 OSC2/CLKO OSC1/CLKI PIC18F44J10 PIC18F45J10 27 RE2/CS/AN7 7 26 RE1/WR/AN6 8 RE0/RD/AN5 RA5/AN4/SS1/C2OUT DDCORE Preliminary /V CAP © 2007 Microchip Technology Inc. ...
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... Appendix A: Revision History............................................................................................................................................................. 341 Appendix B: Migration Between High-End Device Families............................................................................................................... 341 The Microchip Web Site ..................................................................................................................................................................... 353 Customer Change Notification Service .............................................................................................................................................. 353 Customer Support .............................................................................................................................................................................. 353 Reader Response .............................................................................................................................................................................. 354 PIC18F45J10 family Product Identification System ........................................................................................................................... 355 © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682C-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39682C-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... This document contains device specific information for the following devices: • PIC18F24J10 • PIC18LF24J10 • PIC18F25J10 • PIC18LF25J10 • PIC18F44J10 • PIC18LF44J10 • PIC18F45J10 • PIC18LF45J10 This family offers the advantages of all PIC18 microcontrollers – namely, high computational perfor- mance at an economical price. The PIC18F45J10 family ...
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... Parallel Slave Port (present only on 40/44-pin devices). 6. One MSSP module for PIC18F24J10/25J10 devices and 2 PIC18F44J10/45J10 devices 7. Parts designated with an “F” part number (i.e., PIC18F25J10) have a minimum V whereas parts designated with an “LF” part number (i.e., PIC18LF25J10) can operate between 2.0-3.6 volts on V ...
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... Underflow (PWRT, OST), OST), MCLR, WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled Instruction Set enabled 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN Preliminary PIC18F44J10 PIC18F45J10 DC – 40 MHz DC – 40 MHz 16384 32768 8192 16384 768 1536 20 20 Ports Ports ...
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... Reference ADC Timer1 Timer2 10-bit MSSP CCP2 EUSART Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V -/CV REF REF RA3/AN3/V + REF RA5/AN4/SS1/C2OUT PORTB RB0/INT0/FLT0/AN12 RB1/INT1/AN10 RB2/INT2/AN8 (1) RB3/AN9/CCP2 RB4/KBI0/AN11 RB5/KBI1/T0CKI/C1OUT RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI (1) RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK1/SCL1 RC4/SDI1/SDA1 RC5/SDO1 RC6/TX/CK RC7/RX/DT © 2007 Microchip Technology Inc. ...
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... FIGURE 1-2: PIC18F44J10/45J10 (40/44-PIN) BLOCK DIAGRAM Table Pointer<21> 8 inc/dec logic PCLATU PCLATH 21 20 PCU PCH Program Counter 31 Level Stack Address Latch Program Memory STKPTR (16/32 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> IR State Machine Instruction Control Signals Decode and ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary Description © 2007 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP QFN TQFP MCLR 1 18 MCLR OSC1/CLKI 13 32 OSC1 CLKI OSC2/CLKO 14 33 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set. ...
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... TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF RA3/AN3 REF RA3 AN3 V + REF RA5/AN4/SS1/C2OUT 7 24 RA5 AN4 SS1 C2OUT Legend: TTL = TTL compatible input ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RB0/INT0/FLT0/AN12 33 9 RB0 INT0 FLT0 AN12 RB1/INT1/AN10 34 10 RB1 INT1 AN10 RB2/INT2/AN8 35 11 RB2 INT2 AN8 RB3/AN9/CCP2 36 12 RB3 AN9 (1) CCP2 RB4/KBI0/AN11 37 14 RB4 KBI0 ...
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... TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RC0/T1OSO/T1CKI 15 34 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 16 35 RC1 T1OSI (2) CCP2 RC2/CCP1/P1A 17 36 RC2 CCP1 P1A RC3/SCK1/SCL1 18 37 RC3 SCK1 SCL1 RC4/SDI1/SDA1 23 42 RC4 SDI1 SDA1 RC5/SDO1 24 43 ...
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... PIC18F45J10 FAMILY TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RD0/PSP0/SCK2 SCL2 RD0 PSP0 SCK2 SCL2 RD1/PSP1/SDI2/SDA2 20 39 RD1 PSP1 SDI2 SDA2 RD2/PSP2/SDO2 21 40 RD2 PSP2 SDO2 RD3/PSP3/SS2 22 41 RD3 PSP3 SS2 RD4/PSP4 27 2 RD4 ...
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... TABLE 1-3: PIC18F44J10/45J10 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP QFN TQFP RE0/RD/AN5 8 25 RE0 RD AN5 RE1/WR/AN6 9 26 RE1 WR AN6 RE2/CS/AN7 10 27 RE2 CS AN7 DDCORE CAP V DDCORE V CAP NC — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 22 Preliminary © 2007 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 2-1: ( Output (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... OSC2 is not available. FIGURE 2-3: Clock from of external Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F45J10 F /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F45J10 (HS Mode) Open OSC2 © 2007 Microchip Technology Inc. ...
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... Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 2-4: HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 ...
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... Features of the CPU” for Configuration register details. PIC18F45J10 Family HS, EC HSPLL, ECPLL 4 x PLL T1OSC Internal Oscillator INTRC Source FOSC2:FOSC0 Preliminary © 2007 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 2.6.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device’ ...
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... MSSP slave, PSP, INTn pins and others). Peripherals that may add significant current Section 23.2 “DC Characteristics: Power-Down and Supply Current”. Preliminary (1) U-0 R/W-0 R/W-0 — SCS1 SCS0 bit Writable bit consumption are listed © 2007 Microchip Technology Inc. in ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes) ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • the primary clock, as defined by the FOSC1:FOSC0 configuration bits • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run n-1 n Clock Transition Preliminary © 2007 Microchip Technology Inc. ...
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... Note 1024 T . These intervals are not shown to scale. OST OSC © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-3) ...
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... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits OSTS bit Set Preliminary CSD © 2007 Microchip Technology Inc. ...
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... OSC1 CPU Clock Peripheral Clock Program Counter Wake Event © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by set- ting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to ‘ ...
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... T CSD still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. Preliminary © 2007 Microchip Technology Inc. (see Section 3.2 “Run following the wake event is ...
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... PWRT 65.5 ms INTRC 11-bit Ripple Counter Note 1: The Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred ...
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... POR was set to ‘1’ by software immediately after POR). DS39682C-page 38 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY FIGURE 4- Note 1: External Power-on Reset circuit is required ...
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... PWRT will expire. Bringing MCLR high will begin (Figure 4-5). This is useful for testing purposes synchronize more than one PIC18F device operating in parallel. T PWRT T PWRT Preliminary © 2007 Microchip Technology Inc. all depict time-out execution immediately , V RISE < PWRT ): CASE 1 ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE 2 DD ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Preliminary STKPTR Register (2) POR BOR STKFUL STKUNF © 2007 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... Interrupt uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu --u- uuuu © 2007 Microchip Technology Inc. ...
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... NOP instruction). The PIC18F24J10 and PIC18F44J10 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F25J10 and PIC18F45J10 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 © 2007 Microchip Technology Inc. ...
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... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Preliminary nn COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2007 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When ‘a’ The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 7Fh 80h Access RAM High (SFRs) FFh © 2007 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Data Memory 000h ...
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... F90h — (2) F8Fh — F8Eh SSP2BUF (3) F8Dh LATE (3) F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (3) F88h SSP2ADD (1) (3) F87h SSP2STAT (3) F86h SSP2CON1 (3) F85h SSP2CON2 (3) F84h PORTE (3) F83h PORTD F82h PORTC F81h PORTB F80h PORTA © 2007 Microchip Technology Inc. ...
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... Note 1: See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as individual unimplemented bits should be interpreted as ‘-’. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 Top-of-Stack Upper Byte (TOS< ...
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... CCP2M0 45, 123 --00 0000 WUE ABDEN 45, 190 01-0 0-00 (2) (2) PDC1 PDC0 45, 140 0000 0000 (2) (2) PSSBD0 45, 141 0000 0000 CVR1 CVR0 45, 225 0000 0000 CM1 CM0 45, 219 0000 0111 . Reset values are shown for 40/44-pin devices; © 2007 Microchip Technology Inc. ...
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... Note 1: See Section 4.4 “Brown-out Reset (BOR) (PIC18F2X1X/4X1X Devices Only)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as individual unimplemented bits should be interpreted as ‘-’. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 4 Bit 3 Bit 2 Bit 1 ...
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... The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
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... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory © 2007 Microchip Technology Inc. ...
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... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
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... Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory Preliminary © 2007 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F80h by using the BSR. FFFh © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 66 Preliminary © 2007 Microchip Technology Inc. ...
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... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Reading Preliminary Table Latch (8-bit) TABLAT © 2007 Microchip Technology Inc. ...
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... The WR bit can only be set (not cleared) in software Write cycle to the EEPROM is complete bit 0 Unimplemented: Read as ‘0’ Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 R/W-x — — ...
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... Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 Table Erase TBLPTR<21:10> Table Write TBLPTR<21:6> Table Read – TBLPTR<21:0> Preliminary TBLPTRL 0 Table Write TBLPTR<5:0> © 2007 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVFW TABLAT, W MOVF WORD_ODD © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary © 2007 Microchip Technology Inc. ...
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... Set the EECON1 register for the write operation: • set WREN to enable byte writes. 4. Disable interrupts. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
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... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block Preliminary © 2007 Microchip Technology Inc. ...
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... OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 6.5.4 PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 20.0 “ ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 76 Preliminary © 2007 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2007 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Preliminary © 2007 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
Page 83
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 84
... DS39682C-page 82 R/W-1 R/W-1 U-0 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 R/W-0 ...
Page 86
... R-0 R-0 R/W-0 R/W-0 RCIF TXIF SSP1IF CCP1IF ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 87
... BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module bus collision occurred (must be cleared in software bus collision occurred bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 U-0 — — ...
Page 88
... R = Readable bit -n = Value at POR DS39682C-page 86 R/W-0 R/W-0 R/W-0 R/W-0 RCIE TXIE SSP1IE CCP1IE ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown ...
Page 89
... Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module Enabled 0 = Disabled bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-0 U-0 — — BCL1IE — Writable bit U = Unimplemented bit, read as ‘ ...
Page 90
... R = Readable bit -n = Value at POR DS39682C-page 88 R/W-1 R/W-1 R/W-1 R/W-1 RCIP TXIP SSP1IP CCP1IP ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown ...
Page 91
... Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module High priority 0 = Low priority bit 5-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY U-0 U-0 R/W-1 U-0 — — BCL1IP — ...
Page 92
... Legend Readable bit -n = Value at POR DS39682C-page 90 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 8.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 92 Preliminary © 2007 Microchip Technology Inc. ...
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... Port Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
Page 96
... Configure A/D MOVWF ADCON1 ; for digital inputs MOVWF 07h ; Configure comparators MOVWF CMCON ; for digital input MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs Preliminary © 2007 Microchip Technology Inc. - inputs and the com- REF ...
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... Legend: DIG = Digital level output; TTL = TTL input buffer Schmitt Trigger input buffer; ANA = Analog level input/output Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY I/O I/O ...
Page 98
... RA3 RA2 TRISA5 — TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 Preliminary Reset Bit 1 Bit 0 Values on page RA1 RA0 46 46 TRISA1 TRISA0 46 PCFG1 PCFG0 44 CM1 CM0 45 CVR1 CVR0 45 © 2007 Microchip Technology Inc. ...
Page 99
... By programming the configuration bit, PBADEN, RB4:RB0 will alternatively be configured as digital inputs on POR. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Four of the PORTB pins (RB7:RB4) have an interrupt- on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt- on-change comparison) ...
Page 100
... PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-change pin. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Preliminary Description (1) (1) (1) (1) (1) (3) (3) (3) © 2007 Microchip Technology Inc. ...
Page 101
... GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE ...
Page 102
... EXAMPLE 9-4: INITIALIZING PORTC CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches CLRF LATC ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs Preliminary © 2007 Microchip Technology Inc. ...
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... C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3. 2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY I/O ...
Page 104
... RC7 RC6 LATC PORTC Data Latch Register (Read and Write to Data Latch) TRISC PORTC Data Direction Control Register DS39682C-page 102 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Preliminary Reset Bit 1 Bit 0 Values on page RC1 RC0 © 2007 Microchip Technology Inc. ...
Page 105
... Capture/Compare/PWM (ECCP) Module”. Note Power-on Reset, these pins are configured as digital inputs. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 9.7 “ ...
Page 106
... PSP read data output (LATD<7>); takes priority over port data. TTL PSP write data input. DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. I Preliminary 2 2 C/SMB = I C/SMBus input buffer; © 2007 Microchip Technology Inc. ...
Page 107
... TRISE IBF OBF CCP1CON P1M1 P1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 ...
Page 108
... CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 0Ah ; Configure A/D MOVWF ADCON1 ; for digital inputs MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<0> as inputs ; RE<1> as outputs ; RE<2> as inputs Preliminary © 2007 Microchip Technology Inc. ...
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... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY R-0 R/W-0 R/W-0 U-0 OBF IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 110
... RE2 — — — PORTE Data Latch Register (Read and Write to Data Latch) IBOV PSPMODE — TRISE2 VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Description Reset Bit 1 Bit 0 Values on page RE1 RE0 46 46 TRISE1 TRISE0 46 PCFG1 PCFG0 44 © 2007 Microchip Technology Inc. ...
Page 111
... PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The timing for the control signals in Write and Read modes is shown in Figure 9-4 and Figure 9-5, respectively ...
Page 112
... CCP1IF RCIE TXIE SSP1IE CCP1IE RCIP TXIP SSP1IP CCP1IP VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 RE1 RE0 46 46 TRISE1 TRISE0 46 INT0IF RBIF 43 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP 45 PCFG1 PCFG0 44 © 2007 Microchip Technology Inc. ...
Page 113
... Prescale value Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
Page 114
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 115
... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 116
... PIC18F45J10 FAMILY NOTES: DS39682C-page 114 Preliminary © 2007 Microchip Technology Inc. ...
Page 117
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... Special Event Trigger) 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2007 Microchip Technology Inc. ...
Page 119
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary Trigger in Compare mode © 2007 Microchip Technology Inc. ...
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... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 120 Preliminary © 2007 Microchip Technology Inc. ...
Page 123
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 124
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSP1IF CCP1IF TXIE SSP1IE CCP1IE TXIP SSP1IP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 43 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP © 2007 Microchip Technology Inc. ...
Page 125
... CCPx match (CCPxIF bit is set) 11xx = PWM mode Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. Note: Throughout this section and Section 14.0 “ ...
Page 126
... Changing the pin assignment of CCP2 does not auto- matically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2 operation regardless of where it is located. Interaction Preliminary © 2007 Microchip Technology Inc. in Figure 13-1 and ...
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... Prescaler ÷ CCP1CON<3:0> CCP2CON<3:0> CCP2 pin Prescaler ÷ © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 13.2.3 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared ...
Page 128
... Set CCP1IF Compare Output Match Logic 4 CCP1CON<3:0> Special Event Trigger (Timer1 Reset, A/D Trigger) Set CCP2IF Compare Output Match Logic 4 CCP2CON<3:0> Preliminary Special Event Trigger mode CCP1 pin TRIS Output Enable CCP2 pin TRIS Output Enable © 2007 Microchip Technology Inc. ...
Page 129
... CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1. Note 1: These bits are not implemented on 28-pin devices and should be read as ‘0’. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE ...
Page 130
... CCPRxH until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC © 2007 Microchip Technology Inc. ...
Page 131
... The PWM auto-shutdown features of the Enhanced CCP module are also available to CCP1 in 28-pin devices. The operation of this feature is discussed in detail in Section 14.4.7 “Enhanced PWM Auto-Shutdown”. Auto-shutdown features are not available for CCP2. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY EQUATION 13-3: PWM Resolution (max) Note: ...
Page 132
... PSSAC1 PSSAC0 PSSBD1 (1) (1) (1) PDC5 PDC4 PDC3 PDC2 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 43 PD POR BOR 42 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP CCP1M1 CCP1M0 CCP2M1 CCP2M0 45 (1) (1) PSSBD0 45 (1) (1) (1) PDC1 PDC0 45 © 2007 Microchip Technology Inc. ...
Page 133
... ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE Note: The ECCP module is implemented only in 40/44-pin devices. In PIC18F44J10/45J10 devices, implemented as a standard CCP module with Enhanced PWM capabilities. These include the provisions for output channels, user-selectable polarity, dead-band control and automatic shutdown REGISTER 14-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES) ...
Page 134
... PWM. provided in and Timer RC2 RD5 All 40/44-pin Devices: CCP1 RD5/PSP5 P1A P1B P1A P1B Preliminary and Section 13.3 “Compare for PWM Operation” or RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2007 Microchip Technology Inc. ...
Page 135
... CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 14.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
Page 136
... The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 14-2. ) bits 9.77 kHz 39.06 kHz FFh FFh Preliminary 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2007 Microchip Technology Inc. ...
Page 137
... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 14.4.6 “Programmable Dead-Band Delay”). © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
Page 138
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2007 Microchip Technology Inc. ...
Page 139
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<7:5> data latches. The TRISC<2> and TRISD<7:5> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
Page 140
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD © 2007 Microchip Technology Inc. ...
Page 141
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals ...
Page 142
... OSC OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary driving). The ECCPASE bit R/W-0 R/W-0 R/W-0 (1) (1) (1) (1) PDC2 PDC1 PDC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 143
... Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: Reserved on 28-pin devices; maintain these bits clear. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 ( Writable bit U = Unimplemented bit, read as ‘ ...
Page 144
... PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2007 Microchip Technology Inc. ...
Page 145
... Wait until TMRn overflows (TMRnIF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 14.4.10 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 146
... Bit 1 Bit 0 Values on page INT0IF RBIF 43 PD POR BOR 42 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP 45 — — CCP2IF 45 — — CCP2IE 45 — — CCP2IP TMR1CS TMR1ON CCP1M1 CCP1M0 45 (1) (1) PSSBD1 PSSBD0 45 (1) (1) (1) PDC2 PDC1 PDC0 45 © 2007 Microchip Technology Inc. ...
Page 147
... Master mode • Multi-Master mode • Slave mode PIC18F24J10/25J10 (28-pin) devices have one MSSP module designated as MSSP1. PIC18F44J10/45J10 (40/44-pin) devices have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: Throughout this section, generic refer- ...
Page 148
... A write to SSPxBUF will write to both SSPxBUF and SSPxSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary the SSPxBUF is not R-0 R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 149
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ...
Page 150
... Example 15-1 shows the loading of the SSP1BUF transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. Preliminary © 2007 Microchip Technology Inc. register completed (SSP1SR) for data ...
Page 151
... Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 15.3.4 TYPICAL CONNECTION Figure 15-2 shows a typical connection between two microcontrollers ...
Page 152
... SMP bit. The time when the SSPxBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit 1 Preliminary ) Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 153
... SSPxIF Interrupt Flag SSPxSR to SSPxBUF © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application ...
Page 154
... Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS39682C-page 152 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary ) 0 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 155
... EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 15.3.10 BUS MODE COMPATIBILITY Table 15-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 156
... SSPEN CKP SSPM3 SSPM2 D R/W Preliminary Reset Bit 1 Bit 0 Values on page INT0IF RBIF 43 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP 45 — — 45 — — 45 — — 45 TRISA1 TRISA0 46 TRISC1 TRISC0 46 TRISD1 TRISD0 46 44 SSPM1 SSPM0 SSPM1 SSPM0 © 2007 Microchip Technology Inc. ...
Page 157
... Start and Stop bit Detect Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.1 REGISTERS The MSSP module has six registers for I These are: • ...
Page 158
... R = Readable bit -n = Value at POR DS39682C-page 156 2 C™ MODE) R-0 R-0 R-0 D mode only Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R-0 R-0 R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... C Slave mode, 10-bit address 2 0110 = I C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 2 C™ MODE) R/W-0 R/W-0 R/W-0 SSPEN ...
Page 160
... R/W-0 (1) (1) ACKDT ACKEN RCEN PEN ( (1) (1) ( module is not in the Idle mode Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 (1) (1) (1) RSEN SEN bit 0 ( Bit is unknown ...
Page 161
... The high and low times of the specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.3.1 Addressing Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register ...
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... An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682C-page 161 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39682C-page 162 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682C-page 163 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) DS39682C-page 164 Preliminary © 2007 Microchip Technology Inc. ...
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... SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.4.3 Clock Stretching for 7-bit Slave Transmit Mode ...
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... I C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 15-12). Master device asserts clock Master device deasserts clock Preliminary DX – 1 © 2007 Microchip Technology Inc. ...
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... FIGURE 15-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682C-page 167 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) DS39682C-page 168 Preliminary © 2007 Microchip Technology Inc. ...
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... S SSPxIF BF (SSPxSTAT<0>) SSPOV (SSPxCON1<6>) GCEN (SSPxCON2<7>) © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. ...
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... Acknowledge Generate Start bit Detect Stop bit Detect Write Collision Detect Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1) Clock Arbitration Set SSPxIF, BCLxIF State Counter for Reset ACKSTAT, PEN (SSPxCON2) End of XMIT/RCV Preliminary SSPM3:SSPM0 SSPxADD<6:0> Baud Rate Generator © 2007 Microchip Technology Inc. ...
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... SCLx clock frequency for 2 either 100 kHz, 400 kHz or 1 MHz I C operation. See Section 15.4.7 “Baud Rate” for more detail. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2< ...
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... MHz 00h 2 C specification (which applies to rates greater than Preliminary 2 C Master mode OSC F SCL (2 Rollovers of BRG) (1) 400 kHz 312.5 kHz 100 kHz (1) 400 kHz 308 kHz 100 kHz (1) 333 kHz 100 kHz (1) 1 MHz © 2007 Microchip Technology Inc. ...
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... BRG 03h Value BRG Reload © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 15-18) ...
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... SSPxCON2 is disabled until the Start condition is complete. Set S bit (SSPxSTAT<3>) SDAx = 1, At completion of Start bit, SCLx = 1 hardware clears SEN bit and sets SSPxIF bit T T BRG BRG Write to SSPxBUF occurs here 1st bit T BRG T BRG S Preliminary 2nd bit © 2007 Microchip Technology Inc. ...
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... SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit SCLx © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Note 1: If RSEN is programmed while any other event is in progress, it will not take effect bus collision during the Repeated Start 2 ...
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... WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Preliminary DS39682C-page 177 ...
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... PIC18F45J10 FAMILY 2 FIGURE 15-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS39682C-page 178 Preliminary © 2007 Microchip Technology Inc. ...
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... SCLx SDAx ACK Note one Baud Rate Generator period. BRG © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 15.4.13 STOP CONDITION TIMING A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a ...
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... Idle and the S and P bits are cleared. SDAx line pulled low by another source SDAx released by master Preliminary bus bus Sample SDAx. While SCLx is high, data doesn’t match what is driven by the master. Bus collision has occurred. Set bus collision interrupt (BCLxIF) © 2007 Microchip Technology Inc. ...
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... S bit and SSPxIF set because BCLxIF SDAx = 0, SCLx = 1. S SSPxIF © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 15-28). If, however, a ‘1’ is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count ...
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... SDAx = 0, SCLx = 1 Set S Set SSPxIF BRG T BRG S SCLx pulled low after BRG time-out Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SDAx = 0, SCLx = 1, set SSPxIF Preliminary Interrupt cleared in software ‘0’ ‘0’ ‘0’ Interrupts cleared in software © 2007 Microchip Technology Inc. ...
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... BCLxIF set BCLxIF. Release SDAx and SCLx. RSEN S SSPxIF © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 15-29). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from ...
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... T BRG BRG T BRG BRG SCLx goes low before SDAx goes high, set BCLxIF Preliminary Rate Generator is loaded with SDAx sampled T BRG low after T , BRG set BCLxIF ‘0’ ‘0’ T BRG ‘0’ ‘0’ © 2007 Microchip Technology Inc. ...
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... CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY 2 C™ OPERATION ...
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... PIC18F45J10 FAMILY NOTES: DS39682C-page 186 Preliminary © 2007 Microchip Technology Inc. ...
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... Synchronous – Master (half duplex) with selectable clock polarity • Synchronous – Slave (half duplex) with selectable clock polarity © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX/ EUSART: • ...
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... Value at POR DS39682C-page 188 R/W-0 R/W-0 R/W-0 TX9 TXEN SYNC SENDB W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit -n = Value at POR © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY R/W-0 R/W-0 R/W-0 RX9 SREN CREN ...
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... Value at POR DS39682C-page 190 R-1 U-0 R/W-0 R/W-0 — SCKP BRG16 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-0 — WUE ABDEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Legend Don’t care value of SPBRGH:SPBRG register pair © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY tageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared) ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. DS39682C-page 192 Bit 5 Bit 4 Bit 3 Bit 2 TXEN SYNC SENDB BRGH SREN CREN ADDEN FERR — SCKP BRG16 — Preliminary Reset Values Bit 1 Bit 0 on page TRMT TX9D 45 OERR RX9D 45 WUE ABDEN © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F45J10 FAMILY SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (K) (decimal) — ...
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... SPBRG % value (decimal) 832 207 103 25 12 — — — — © 2007 Microchip Technology Inc. ...
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... RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character ...
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... RX pin ABDOVF bit BRG Value XXXXh DS39682C-page 196 Edge #1 Edge #2 Edge #3 Bit 3 Start Bit 1 Bit 0 Bit 2 Bit 4 XXXXh XXXXh Start Bit 0 0000h Preliminary 001Ch Edge #4 Edge #5 Bit 5 Bit 7 Stop Bit Bit 6 Auto-Cleared 1Ch 00h FFFFh 0000h © 2007 Microchip Technology Inc. ...
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... TXEN BRG16 SPBRGH SPBRG Baud Rate Generator © 2007 Microchip Technology Inc. PIC18F45J10 FAMILY Once the TXREG register transfers the data to the TSR register (occurs in one T and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1< ...
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... Preliminary bit 7/8 Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. Reset Bit 1 Bit 0 Values on page INT0IF RBIF 43 TMR2IF TMR1IF 45 TMR2IE TMR1IE 45 TMR2IP TMR1IP 45 OERR RX9D 45 45 TRMT TX9D 45 WUE ABDEN © 2007 Microchip Technology Inc. ...