PIC16C771-I/SO Microchip Technology, PIC16C771-I/SO Datasheet - Page 88
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PIC16C771-I/SO
Manufacturer Part Number
PIC16C771-I/SO
Description
IC MCU OTP 4KX14 A/D PWM 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C771-I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
15
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
PIC16C
No. Of I/o's
16
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16C771I/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PIC16C717/770/771
9.2.11
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is set high while the I
in the idle state. When the RSEN bit is set, the SCL pin
is asserted low. When the SCL pin is sampled low, the
baud rate generator is loaded with the contents of
SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (T
if SDA is sampled high, the SCL pin will be de-asserted
(brought high). When SCL is sampled high, the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one T
is then followed by assertion of the SDA pin (SDA is
low) for one T
a START condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. Following
this, the baud rate generator is reloaded with the con-
tents of SSPAD<6:0> and begins counting. When the
BRG times out a third time, the RSEN bit in the
SSPCON2 register is automatically cleared and SCL is
pulled low. The SSPIF flag is set, which indicates the
Restart sequence is complete.
FIGURE 9-17:
DS41120B-page 86
Note 1: If RSEN is set while another event is in
BRG
2: A bus collision during the Repeated
I
START CONDITION TIMING
). When the baud rate generator times out,
progress, it will not take effect. Queuing of
events is not allowed.
2
START condition occurs if either of the
following is true:
a) SDA is sampled low when SCL
b) SCL goes low before SDA is
C MASTER MODE REPEATED
BRG
Falling edge of ninth clock
goes from low to high.
asserted low. This may indicate
that another master is attempting
to transmit a data “1”.
period while SCL is high. As soon as
REPEAT START CONDITION WAVEFORM
SDA
SCL
End of Xmit
BRG
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
period. This action
2
C module is
Advance Information
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit transition to true,
the user may write the SSPBUF with the 7-bit address
in 7-bit mode, or the default first address in 10-bit
mode. After the first eight bits are transmitted and an
ACK is received, the user may then perform one of the
following:
• Transmit an additional eight bits of address (if the
• Transmit eight bits of data (if the user transmitted
• Receive eight bits of data (if the user transmitted
9.2.11.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
user transmitted the first half of a 10-bit address
with R/W = 0),
a 7-bit address with R/W = 0), or
either the first half of a 10-bit address or a 7-bit
address with R/W = 1).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clears RSEN bit
Set S (SSPSTAT<3>)
WCOL STATUS FLAG
Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and sets SSPIF
Write to SSPBUF occurs here.
T
BRG
1st Bit
T
BRG
2002 Microchip Technology Inc.