PIC16LC717-I/SO Microchip Technology, PIC16LC717-I/SO Datasheet - Page 95
![IC MCU OTP 2KX14 A/D PWM 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LC717-I/SO
Manufacturer Part Number
PIC16LC717-I/SO
Description
IC MCU OTP 2KX14 A/D PWM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC717-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LC717I/SO
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9.2.16
Clock arbitration occurs when the master, during any
receive, transmit or repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
FIGURE 9-22:
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
2002 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
T
BRG
Advance Information
SCL line sampled once every machine cycle (Tosc
Hold off BRG until SCL is sampled high.
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-22).
PIC16C717/770/771
T
BRG
SCL = 1 BRG starts counting
clock high interval.
DS41120B-page 93
4).
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