PIC16C716-04I/SS Microchip Technology, PIC16C716-04I/SS Datasheet - Page 19
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PIC16C716-04I/SS
Manufacturer Part Number
PIC16C716-04I/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16C716-04I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-8:
© 2005 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
bit 1:
bit 0:
U-0
—
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode:
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIR1 Register
R/W-0
ADIF
PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
U-0
—
R/W-0
—
CCP1IF
R/W-0
TMR2IF
R/W-0
Note:
TMR1IF
R/W-0
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
PIC16C712/716
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
-n = Value at POR Reset
read as ‘0’
DS41106B-page 17