PIC16F627-20E/SO Microchip Technology, PIC16F627-20E/SO Datasheet - Page 106

• Manufacturer Part Number: PIC16F627-20E/SO
• Description: IC MCU FLASH 1KX14 18-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627-20E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

PIC16F62X
FIGURE 14-16:
TABLE 14-10: SUMMARY OF WATCHDOG TIMER REGISTERS
14.9
The Power-down mode is entered by executing a
SLEEP
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before
impedance).
DS40300C-page 104
2007h
81h
Legend:
Note
Address
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
1: Shaded cells are not used by the Watchdog Timer.
SLEEP
instruction.
Power-Down Mode (SLEEP)
_
= Unimplemented location, read as “0”, + = Reserved for future use
Config.
bits
OPTION
Name
was executed (driving high, low, or hi-
Enable Bit
Watchdog
WATCHDOG TIMER BLOCK DIAGRAM
RBPU
Bit 7
Timer
WDT
LVP
From TMR0 Clock Source
INTEDG
BODEN
(Figure 6-1)
Bit 6
MCLRE
T0CS
Bit 5
PSA
0
1
M
U
X
FOSC2
T0SE
Preliminary
Bit 4
PWRTE
Bit 3
PSA
WDT POSTSCALER/
TMR0 PRESCALER
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the com-
parators, and V
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
0
SS
Timeout
Note:
MUX
WDT
8 to 1 MUX
WDTE
for lowest current consumption. The contribution
Bit 2
PS2
1
8
It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
FOSC1
Bit 1
PS1
REF
PSA
3
(Figure 6-1)
should be disabled. I/O pins that
PS<2:0>
To TMR0
FOSC0
 2003 Microchip Technology Inc.
Bit 0
PS0
DD
, or V
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
POR Reset
Value on
SS
, with no external
Value on all
RESETS
IHMC
other
DD
).
or