PIC16LF819T-I/SS Microchip Technology, PIC16LF819T-I/SS Datasheet - Page 210
![IC MCU FLASH 2KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16LF819T-I/SS
Manufacturer Part Number
PIC16LF819T-I/SS
Description
IC MCU FLASH 2KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 210 of 324
- Download datasheet (6Mb)
PIC18F2450/4450
18.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 18-5:
TABLE 18-3:
DS39760D-page 208
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
®
microcontrollers.
File Name
Program Verification and
Code Protection
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
(PIC18F2450/4450)
Unimplemented
Unimplemented
Unimplemented
16 Kbytes
Boot Block
Read ‘0’s
Read ‘0’s
Read ‘0’s
Block 0
Block 1
Bit 7
—
—
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
000000h
0007FFh
000FFFh
001000h
001FFFh
002000h
003FFFh
1FFFFFh
Address
WRTC
Range
Bit 5
—
—
—
—
—
Each of the three blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
Bit 4
—
—
—
—
—
—
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
Bit 3
—
—
—
—
—
—
Controlled By:
Bit 2
© 2008 Microchip Technology Inc.
—
—
—
—
—
—
EBTR1
WRT1
Bit 1
CP1
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—
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