PIC12C671-10I/MF Microchip Technology, PIC12C671-10I/MF Datasheet - Page 304
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PIC12C671-10I/MF
Manufacturer Part Number
PIC12C671-10I/MF
Description
IC MCU OTP 1KX14 A/D 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C671-10I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C67110I/MF
- Current page: 304 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.5
DS31017A-page 17-28
SDA
SCL
Master Mode
Master mode of operation is supported by interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP
module is disabled. Control of the I
with both the S and P bits clear.
In master mode the SCL and SDA lines are manipulated by the SSP hardware.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated Start
Figure 17-17: SSP Block Diagram (I 2 C Master Mode)
SDA in
Bus Collision
SCL in
Read
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock Arbitration
Start bit detect
Stop bit detect
Acknowledge
Generate
SSPBUF
SSPSR
Preliminary
2
C bus may be taken when the P bit is set, or the bus is idle
LSb
Write
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1997 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0
Baud
rate
generator
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