PIC16LF72-I/SS Microchip Technology, PIC16LF72-I/SS Datasheet - Page 17
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PIC16LF72-I/SS
Manufacturer Part Number
PIC16LF72-I/SS
Description
IC PIC MCU FLASH 2KX14 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F72-ISO.pdf
(136 pages)
4.PIC16F72-ISO.pdf
(136 pages)
Specifications of PIC16LF72-I/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC16LF
No. Of I/o's
22
Ram Memory Size
128Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF72-I/SS
Manufacturer:
Microchi
Quantity:
92 666
Part Number:
PIC16LF72-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
2002 Microchip Technology Inc.
Note:
bit 7
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 Register
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
bit 7
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
Unimplemented: Read as ‘0’
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
- n = Value at POR
U-0
—
R/W-0
ADIE
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPIE
R/W-0
CCP1IE
R/W-0
PIC16F72
x = Bit is unknown
TMR2IE
R/W-0
DS39597B-page 15
TMR1IE
R/W-0
bit 0