PIC16C771/SO Microchip Technology, PIC16C771/SO Datasheet - Page 2

• Manufacturer Part Number: PIC16C771/SO
• Description: IC MCU OTP 4KX14 A/D PWM 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C771/SO

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164028 - MODULE SKT PROMATEII 20SOIC/DIP309-1013 - ADAPTER 20-SOIC TO 20-DIP309-1012 - ADAPTER 20-SOIC TO 20-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16C717/770/771
3.
TABLE 1: DC SPECIFICATION DEVIATIONS FROM DATA SHEET
TABLE 2: DC SPECIFICATION DEVIATIONS FROM DATA SHEET
DS80100C-page 2
D005
Param
Param
D420
No.
No.
Module: ECCP (Compare Mode)
The CCP1 output latch, observed on RB3/CCP1/
P1A, can change unexpectedly when the ECCP
module is changed from a set output on match
(CCP1CON<3:0> = “1000”) to clear output on
match (CCP1CON<3:0> = “1001”) or vice versa.
This condition will occur, following an ECCP
Reset, at the third iteration of the following
sequence:
1.
2.
Step 1 of the third iteration will cause the CCP1
output latch to immediately, and erroneously,
change to the inverse of the CCPR1<0> bit. This
gives the appearance of an inverted ECCP
response to the third, and subsequent, compare
match events.
CCPR1<3:0> is changed from “1001” to
“1000” or vice versa.
The TMR1H:TMR1L register pair matches
the CCP1R1H:CCPR1L register pair.
V
Sym.
Sym.
V
BOR
LVD
BOR Voltage
LVD Voltage
Characteristic
Characteristic
BORV<1:0> = 0100
BORV<1:0> = 0101
BORV<1:0> = 0110
BORV<1:0> = 0111
LVV<3:0> = 0100
LVV<3:0> = 0101
LVV<3:0> = 0110
LVV<3:0> = 0111
LVV<3:0> = 1000
LVV<3:0> = 1001
LVV<3:0> = 1010
LVV<3:0> = 1011
LVV<3:0> = 1100
LVV<3:0> = 1101
LVV<3:0> = 1110
Tested Specification
Tested Specification
2.35
2.55
3.95
4.23
2.35
2.55
2.64
2.83
3.11
3.29
3.39
3.58
3.77
3.95
4.23
Min
Min
The apparent inverted response will persist until
the CCP1CON<3> bit is cleared (exiting Compare
mode). Interrupts always occur correctly on the
match condition. The error is only in the state of the
CCP1 output latch.
Work around
Option 1
Use the ECCP toggle output on compare match
mode (CCP1CON<3:0> = “0010”).
Option 2
Do not selectively change the CCP1CON<0> bit.
Instead, perform the following:
• Set the RB3 data latch to the same state as
• Next, clear the CCP1CON register (clrf
• Finally, set the CCP1CON<3:0> bits to the
the CCP1 output latch (movf PORTB, f) to
avoid an output glitch when the CCP1CON
register is cleared.
CCP1CON).
next desired output on Compare Match
mode.
Typ
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
2.80
3.02
4.71
5.05
Max
2.80
3.02
3.14
3.37
3.71
3.93
4.04
4.26
4.49
4.71
5.05
Min
Min
2.5
2.7
4.2
4.5
2.5
2.7
2.8
3.0
3.3
3.5
3.6
3.8
4.0
4.2
4.5
2002 Microchip Technology Inc.
Specification
Specification
Data Sheet
Data Sheet
Typ
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
2.66
2.86
4.46
4.78
Max
2.66
2.86
2.98
3.52
3.72
3.84
4.04
4.26
4.46
4.78
3.2
Units
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V