ATMEGA8515-16JUR Atmel, ATMEGA8515-16JUR Datasheet - Page 113

• Manufacturer Part Number: ATMEGA8515-16JUR
• Description: MCU AVR 8KB FLASH 16MHZ 44PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515-16JUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Phase Correct PWM Mode
2512K–AVR–01/10
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1,
2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation
option. The phase correct PWM mode is, like the phase and frequency correct PWM
mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output
mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1
and OCR1x while upcounting, and set on the Compare Match while downcounting. In
inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the
symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or
OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to
MAX). The PWM resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches
either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the
value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter
has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM
mode is shown on Figure 54. The figure shows phase correct PWM mode when OCR1A
or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a
histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-
sent Compare Matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be
set when a Compare Match occurs.
Figure 54. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCnx
OCnx
Period
1
R
PCPWM
2
=
log
---------------------------------- -
(
log
TOP
3
2 ( )
+
1
)
ATmega8515(L)
4
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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