PIC12C672-04E/MF Microchip Technology, PIC12C672-04E/MF Datasheet - Page 130
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PIC12C672-04E/MF
Manufacturer Part Number
PIC12C672-04E/MF
Description
IC PIC MCU 2KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-04E/MF
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DFN
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
- Current page: 130 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
8.2.3
DS31008A-page 8-8
PIR Register(s)
bit
bit
bit
bit
bit
bit
bit
bit
Depending on the number of peripheral interrupt sources, there may be multiple Peripheral Inter-
rupt Flag registers (PIR1, PIR2). These registers contain the individual flag bits for the peripheral
interrupts. These registers will be generically referred to as PIR.
Although, the PIR bits have a general bit location within each register, future devices may not be
able to be consistent with that. It is recommended that you use the supplied Microchip Include
files for the symbolic use of these bits. This will allow the Assembler/Compiler to automatically
take care of the placement of these bits within the specified register.
Register 8-3:
bit 7
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
0 = Waiting to transmit/receive
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
Note 1: Interrupt flag bits get set when an interrupt condition occurs regardless of the state
Note 2: User software should ensure the appropriate interrupt flag bits are cleared (by soft-
of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
ware) prior to enabling an interrupt, and after servicing that interrupt.
PIR Register
(Note 1)
R/W-0
1997 Microchip Technology Inc.
bit 0
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