PIC16LF819T-I/SO Microchip Technology, PIC16LF819T-I/SO Datasheet - Page 235
PIC16LF819T-I/SO
Manufacturer Part Number
PIC16LF819T-I/SO
Description
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MITSUBISHI
Quantity:
330
Part Number:
PIC16LF819T-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 235 of 324
- Download datasheet (6Mb)
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
If CNT
Q1
Q1
Q1
PC =
PC =
=
=
=
≠
register ‘f’
operation
operation
operation
Decrement f, Skip if 0
DECFSZ f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest,
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT – 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
by a 2-word instruction.
11da
operation
operation
operation
DECFSZ
GOTO
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
TEMP
TEMP
If TEMP
If TEMP
PIC18F2450/4450
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Decrement f, Skip if Not 0
DCFSNZ
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – 1 → dest,
skip if result ≠ 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 19.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
3 cycles if skip and followed
by a 2-word instruction.
=
=
=
=
≠
=
DCFSNZ
:
:
f {,d {,a}}
11da
operation
operation
operation
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
Process
Data
No
No
No
Q3
Q3
Q3
DS39760D-page 233
TEMP, 1, 0
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
Related parts for PIC16LF819T-I/SO
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC MCU FLASH 2KX14 EEPROM 18SOIC
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC MCU FLASH 2KX14 EEPROM 20SSOP
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC MCU FLASH 2KX14 EEPROM 28QFN
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC PIC MCU FLASH 2KX14 18SOIC
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC PIC MCU FLASH 2KX14 28QFN
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC MCU FLASH 2KX14 EEPROM 18DIP
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC MCU FLASH 2KX14 18SOIC
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC PIC MCU FLASH 2KX14 20SSOP
Manufacturer:
Microchip Technology
Part Number:
Description:
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC, 8BIT MCU, PIC16LF, 32MHZ, DIP-18
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
IC, 8BIT MCU, PIC16LF, 20MHZ, TQFP-44
Manufacturer:
Microchip Technology
Datasheet:
Part Number:
Description:
7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer:
Microchip Technology