ATMEGA8515-16MUR Atmel, ATMEGA8515-16MUR Datasheet - Page 193
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ATMEGA8515-16MUR
Manufacturer Part Number
ATMEGA8515-16MUR
Description
MCU AVR 8KB FLASH 16MHZ 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8515L-8MC.pdf
(257 pages)
Specifications of ATMEGA8515-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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Serial Programming Pin
Mapping
2512K–AVR–01/10
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed.
Note:
Table 92. Pin Mapping Serial Programming
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 92 on page 193, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
Figure 84. Serial Programming and Verify
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
Symbol
In Table 92, the pin mapping for SPI programming is listed. Not all parts use the SPI pins
dedicated for the internal SPI interface.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
MOSI
MISO
SCK
source to the XTAL1 pin.
MOSI
MISO
SCK
Pins
PB5
PB6
PB7
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
XTAL1
RESET
GND
(1)
I/O
O
I
I
Serial data in
Serial data out
VCC
Description
Serial clock
ATmega8515(L)
ck
ck
≥ 12 MHz
≥ 12 MHz
193
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