PIC18F24J10-I/SS Microchip Technology, PIC18F24J10-I/SS Datasheet - Page 124

• Manufacturer Part Number: PIC18F24J10-I/SS
• Description: IC PIC MCU FLASH 8KX16 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F24J10-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F45J10 FAMILY
12.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 12-1:
TABLE 12-1:
DS39682C-page 122
INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1:
Name
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
F
OSC
Timer2 Interrupt
/4
Timer2 Register
Timer2 Period Register
These bits are not implemented on 28-pin devices and should be read as ‘0’.
PSPIF
PSPIE
PSPIP
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
(1)
(1)
(1)
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
TIMER2 BLOCK DIAGRAM
Internal Data Bus
ADIF
ADIE
ADIP
1:1, 1:4, 1:16
Bit 6
2
Prescaler
TMR0IE
RCIE
RCIP
RCIF
Bit 5
4
TMR2
INT0IE
Bit 4
TXIF
TXIE
TXIP
Preliminary
Reset
8
SSP1IE
SSP1IP
SSP1IF
RBIE
Bit 3
12.3
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 15.0
“Master Synchronous Serial Port (MSSP) Module”.
Comparator
1:1 to 1:16
Postscaler
8
TMR2/PR2
Match
Timer2 Output
TMR0IF
CCP1IE
CCP1IP
CCP1IF
Bit 2
TMR2IF
TMR2IE
TMR2IP
INT0IF
© 2007 Microchip Technology Inc.
Bit 1
PR2
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
TMR1IE
TMR1IP
TMR1IF
Bit 0
RBIF
on page
Values
Reset
43
45
45
45
44
44
44