ATMEGA88PA-MMH Atmel, ATMEGA88PA-MMH Datasheet - Page 242
![MCU AVR 8KB FLASH IND 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA88PA-MMH
Manufacturer Part Number
ATMEGA88PA-MMH
Description
MCU AVR 8KB FLASH IND 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88PA-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88PA-MMH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA88PA-MMHR
Manufacturer:
MTK
Quantity:
101
Part Number:
ATMEGA88PA-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
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21.9
21.9.1
21.9.2
8271C–AVR–08/10
Register Description
TWBR – TWI Bit Rate Register
TWCR – TWI Control Register
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
This is summarized in
Figure 21-21. Possible Status Codes Caused by Arbitration
• Bits 7...0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 222
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
(0xB8)
Read/Write
Initial Value
Bit
(0xBC)
Read/Write
Initial Value
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
START
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
Address / General Call
Figure
Direction
received
Own
TWBR6
TWEA
R/W
R/W
Yes
Arbitration lost in SLA
6
0
6
0
SLA
21-21. Possible status values are given in circles.
Write
Read
TWBR5
TWSTA
R/W
R/W
No
5
0
5
0
TWSTO
TWBR4
R/W
R/W
4
0
4
0
68/78
38
B0
Arbitration lost in Data
TWBR3
TWWC
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
R/W
R
3
0
3
0
Data
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
”Bit Rate Generator
TWBR0
TWIE
R/W
R/W
0
0
0
0
STOP
TWBR
TWCR
242
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